- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377001 > DSP56858VF120 (飛思卡爾半導(dǎo)體(中國)有限公司) 16-bit Digital Signal Controllers PDF資料下載
參數(shù)資料
| 型號： | DSP56858VF120 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號控制器 |
| 文件頁數(shù)： | 17/64頁 |
| 文件大?。?/td> | 956K |
| 代理商： | DSP56858VF120 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
Introduction
56858 Technical Data, Rev. 6
Freescale Semiconductor
17
MODE B
GPIOH1
F3
18
Input
Input/Output
Mode Select (MODE B)
—During the bootstrap process MODE A
selects one of the eight bootstrap modes.
Port H GPIO (1)
—This pin is a General Purpose I/O (GPIO) pin after
the bootstrap process has completed.
MODE C
GPIOH2
F2
19
Input
Input/Output
Mode Select (MODE C)
—During the bootstrap process MODE A
selects one of the eight bootstrap modes.
Port H GPIO (2)
—This pin is a General Purpose I/O (GPIO) pin after
the bootstrap process has completed.
RESET
K4
39
Input
Reset (RESET)
—This input is a direct hardware reset on the
processor. When RESET is asserted low, the device is initialized and
placed in the Reset state. A Schmitt trigger input is used for noise
immunity. When the RESET pin is deasserted, the initial chip operating
mode is latched from the MODE A, MODE B, and MODE C pins.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware reset is required and it is necessary not
to reset the JTAG/Enhanced OnCE module. In this case, assert
RESET, but do not assert TRST.
RSTO
K3
38
Output
Reset Output (RSTO)
—This output is asserted on any reset condition
(external reset, low voltage, software, or COP).
RXD0
GPIOE0
L10
73
Input
Input/Output
Serial Receive Data 0 (RXD0)
—This input receives byte-oriented
serial data and transfers it to the SCI 0 receive shift register.
Port E GPIO (0)
—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
TXD0
GPIOE1
L11
74
Output(Z)
Input/Output
Serial Transmit Data 0 (TXD0)
—This signal transmits data from the
SCI 0 transmit data register.
Port E GPIO (1)
—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
RXD1
GPIOE2
B11
107
Input
Input/Output
Serial Receive Data 1 (RXD1)
—This input receives byte-oriented
serial data and transfers it to the SCI 1 receive shift register.
Port E GPIO (2)
—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
TXD1
GPIOE3
C10
108
Output(Z)
Input/Output
Serial Transmit Data 1 (TXD1)
—This signal transmits data from the
SCI 1 transmit data register.
Port E GPIO (3)
—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
Table 3-1 56858 Signal and Package Information for the 144-pin LQFP and MAPBGA
Signal
Name
BGA
Pin No.
LQFP
Pin No.
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP5685XEVMUM | Feature Phone Software Application Product Brief |
| DSP5685XUM | Feature Phone Software Application Product Brief |
| DSP56F800ERM | Feature Phone Software Application Product Brief |
| DSP56F801FA60E | 16-bit Digital Signal Controllers |
| DSP56F801FA80E | 16-bit Digital Signal Controllers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP5685XEVMUM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Feature Phone Software Application Product Brief |
| DSP5685XSFPPB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Feature Phone Software Application |
| DSP5685XUM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP5685XUMAD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP5685XUMAD Rev 2.0 Addendum |
| DSP56ADC16D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 16-Bit |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。