參數(shù)資料
型號(hào): DSP56366UM
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類: 數(shù)字信號(hào)處理
英文描述: 24-Bit Audio Digital Signal Processor
中文描述: 24位音頻數(shù)字信號(hào)處理器
文件頁數(shù): 81/110頁
文件大小: 1273K
代理商: DSP56366UM
DSP56366 Technical Data, Rev. 3.1
Freescale Semiconductor
3-55
444
Flags input setup before RXC falling
edge
0.0
19.0
x ck
i ck s
ns
445
Flags input hold time after RXC falling
edge
6.0
0.0
x ck
i ck s
ns
446
TXC rising edge to FST out (bl) high
29.0
15.0
x ck
i ck
ns
447
TXC rising edge to FST out (bl) low
31.0
17.0
x ck
i ck
ns
448
TXC rising edge to FST out (wr) high
6
31.0
17.0
x ck
i ck
ns
449
TXC rising edge to FST out (wr) low
6
33.0
19.0
x ck
i ck
ns
450
TXC rising edge to FST out (wl) high
30.0
16.0
x ck
i ck
ns
451
TXC rising edge to FST out (wl) low
31.0
17.0
x ck
i ck
ns
452
TXC rising edge to data out enable from
high impedance
31.0
17.0
x ck
i ck
ns
453
TXC rising edge to transmitter #0 drive
enable assertion
34.0
20.0
x ck
i ck
ns
454
TXC rising edge to data out valid
23 + 0.5
×
T
C
21.0
27.2
21.0
x ck
i ck
ns
455
TXC rising edge to data out high
impedance
7
31.0
16.0
x ck
i ck
ns
456
TXC rising edge to transmitter #0 drive
enable deassertion
7
34.0
20.0
x ck
i ck
ns
457
FST input (bl, wr) setup time before TXC
falling edge
6
2.0
21.0
x ck
i ck
ns
458
FST input (wl) to data out enable from
high impedance
27.0
ns
459
FST input (wl) to transmitter #0 drive
enable assertion
31.0
ns
Table 3-22 Enhanced Serial Audio Interface Timing (continued)
No.
Characteristics
1, 2, 3
Symbol
Expression
Min
Max
Condition
4
Unit
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