參數(shù)資料
型號(hào)： DSP56366UM
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： 24-Bit Audio Digital Signal Processor
中文描述： 24位音頻數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 10/110頁(yè)
文件大小： 1273K
代理商： DSP56366UM
DSP56366 Technical Data, Rev. 3.1
2-6
Freescale Semiconductor
TA
Input
Ignored Input
Transfer Acknowledge
—If the DSP is the bus master and there is no external
bus activity, or the DSP is not the bus master, the TA input is ignored. The TA
input is a data transfer acknowledge (DTACK) function that can extend an
external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be
added to the wait states inserted by the BCR by keeping TA deasserted. In
typical operation, TA is deasserted at the start of a bus cycle, is asserted to
enable completion of the bus cycle, and is deasserted before the next bus cycle.
The current bus cycle completes one clock period after TA is asserted
synchronous to the internal system clock. The number of wait states is
determined by the TA input or by the bus control register (BCR), whichever is
longer. The BCR can be used to set the minimum number of wait states in
external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at least
one wait state. A zero wait state access cannot be extended by TA deassertion,
otherwise improper operation may result. TA can operate synchronously or
asynchronously, depending on the setting of the TAS bit in the operating mode
register (OMR).
TA functionality may not be used while performing DRAM type accesses,
otherwise improper operation may result.
BR
Output
Output
(deasserted)
Bus Request
—BR is an active-low output, never tri-stated. BR is asserted
when the DSP requests bus mastership. BR is deasserted when the DSP no
longer needs the bus. BR may be asserted or deasserted independent of
whether the DSP56366 is a bus master or a bus slave. Bus “parking” allows BR
to be deasserted even though the DSP56366 is the bus master. (See the
description of bus “parking” in the BB signal description.) The bus request hold
(BRH) bit in the BCR allows BR to be asserted under software control even
though the DSP does not need the bus. BR is typically sent to an external bus
arbitrator that controls the priority, parking, and tenure of each master on the
same external bus. BR is only affected by DSP requests for the external bus,
never for the internal bus. During hardware reset, BR is deasserted and the
arbitration is reset to the bus slave state.
Table 2-7 External Bus Control Signals (continued)
Signal Name
Type
State during
Reset
Signal Description
相關(guān)PDF資料
PDF描述
DSP56367P 24-Bit Audio Digital Signal Processor
DSP56367UM 24-Bit Audio Digital Signal Processor
DSP56600 Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
DSP56852E 16-bit Digital Signal Controllers
DSP56852VFE 16-bit Digital Signal Controllers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56367 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic
DSP56367P 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56367UM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor
DSP56371 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device
DSP56371AF180 制造商:Freescale Semiconductor 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*