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參數(shù)資料
| 型號： | DSP56366UM |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-Bit Audio Digital Signal Processor |
| 中文描述： | 24位音頻數(shù)字信號處理器 |
| 文件頁數(shù)： | 18/110頁 |
| 文件大小： | 1273K |
| 代理商： | DSP56366UM |
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DSP56366 Technical Data, Rev. 3.1
2-14
Freescale Semiconductor
2.9
Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals
Signal
Name
Signal Type
State during
Reset
Signal Description
HCKR
Input or output
GPIO
disconnected
High Frequency Clock for Receiver
—When programmed as an input, this
signal provides a high frequency clock source for the ESAI receiver as an
alternate to the DSP core clock. When programmed as an output, this signal
can serve as a high-frequency sample clock (e.g., for external digital to analog
converters [DACs]) or as an additional system clock.
PC2
Input, output, or
disconnected
GPIO
disconnected
Port C 2
—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
HCKT
Input or output
GPIO
disconnected
High Frequency Clock for Transmitter
—When programmed as an input,
this signal provides a high frequency clock source for the ESAI transmitter as
an alternate to the DSP core clock. When programmed as an output, this
signal can serve as a high frequency sample clock (e.g., for external DACs)
or as an additional system clock.
PC5
Input, output, or
disconnected
GPIO
disconnected
Port C 5
—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
FSR
Input or output
GPIO
disconnected
Frame Sync for Receiver
—This is the receiver frame sync input/output
signal. In the asynchronous mode (SYN=0), the FSR pin operates as the
frame sync input or output used by all the enabled receivers. In the
synchronous mode (SYN=1), it operates as either the serial flag 1 pin
(TEBE=0), or as the transmitter external buffer enable control (TEBE=1,
RFSD=1).
When this pin is configured as serial flag pin, its direction is determined by the
RFSD bit in the RCCR register. When configured as the output flag OF1, this
pin will reflect the value of the OF1 bit in the SAICR register, and the data in
the OF1 bit will show up at the pin synchronized to the frame sync in normal
mode or the slot in network mode. When configured as the input flag IF1, the
data value at the pin will be stored in the IF1 bit in the SAISR register,
synchronized by the frame sync in normal mode or the slot in network mode.
PC1
Input, output, or
disconnected
GPIO
disconnected
Port C 1
—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input is 5 V tolerant.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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| DSP56367P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56367UM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56371 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:high density CMOS device |
| DSP56371AF180 | 制造商:Freescale Semiconductor 功能描述: |
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