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| 型號： | DSP56311VL150R2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 53/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP 24BIT 150MHZ 196-MAPBGA |
| 標準包裝： | 1 |
| 系列： | DSP56K/Symphony |
| 類型： | 定點 |
| 接口： | 主機接口，SSI，SCI |
| 時鐘速率： | 150MHz |
| 非易失內(nèi)存： | ROM（576 B） |
| 芯片上RAM： | 384kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.80V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 196-LBGA |
| 供應(yīng)商設(shè)備封裝： | 196-MAPBGA（15x15） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | DSP56311VL150R2CT |
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AC Electrical Characteristics
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-37
2.4.10.2 With an Operating Frequency above 100 MHz
The following considerations can be helpful when GPIO is used for output or input with an operating frequency
above 100 MHz (that is, when CLKOUT is not available).
GPIO as Output:
— The time from fetch of the instruction that changes the GPIO pin to the actual change is seven core
clock cycles. This is true, assuming that the instruction is a one-cycle instruction and that there are no
pipeline stalls or any other pipeline delays.
— The maximum rise or fall time of a GPIO pin is 13 ns (TTL levels, assuming that the maximum of 50
pF load limit is met).
GPIO as Input—GPIO inputs are not synchronized with the core clock. When only one GPIO bit is polled,
this lack of synchronization presents no problem, since the read value can be either the previous value or
the new value of the corresponding GPIO pin. However, there is the risk of reading an intermediate state if:
— Two or more GPIO bits are treated as a coupled group (for example, four possible status states encoded
in two bits).
— The read operation occurs during a simultaneous change of GPIO pins (for example, the change of 00
to 11 may happen through an intermediate state of 01 or 10).
Therefore, when GPIO bits are read, the recommended practice is to poll continuously until two
consecutive read operations have identical results.
2.4.11 JTAG Timing
Table 2-19.
JTAG Timing
No.
Characteristics
All frequencies
Unit
Min
Max
500
TCK frequency of operation (1/(T
C ×
3); maximum 22 MHz)
0.0
22.0
MHz
501
TCK cycle time in Crystal mode
45.0
—
ns
502
TCK clock pulse width measured at 1.5 V
20.0
—
ns
503
TCK rise and fall times
0.0
3.0
ns
504
Boundary scan input data set-up time
5.0
—
ns
505
Boundary scan input data hold time
24.0
—
ns
506
TCK low to output data valid
0.0
40.0
ns
507
TCK low to output high impedance
0.0
40.0
ns
508
TMS, TDI data set-up time
5.0
—
ns
509
TMS, TDI data hold time
25.0
—
ns
510
TCK low to TDO data valid
0.0
44.0
ns
511
TCK low to TDO high impedance
0.0
44.0
ns
512
TRST assert time
100.0
—
ns
513
TRST set-up time to TCK low
40.0
—
ns
Notes:
1.
VCCQH = 3.3 V ± 0.3 V, VCC = 1.8 V ± 0.1 V; TJ = –40°C to +100 °C, CL = 50 pF.
2.
All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
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