參數(shù)資料
型號(hào)： DSP56311VL150R2
廠商： Freescale Semiconductor
文件頁數(shù)： 20/96頁
文件大小： 0K
描述： IC DSP 24BIT 150MHZ 196-MAPBGA
標(biāo)準(zhǔn)包裝： 1
系列： DSP56K/Symphony
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 150MHz
非易失內(nèi)存： ROM（576 B）
芯片上RAM： 384kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.80V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 196-LBGA
供應(yīng)商設(shè)備封裝： 196-MAPBGA（15x15）
包裝： 剪切帶 (CT)
其它名稱： DSP56311VL150R2CT
AC Electrical Characteristics
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
2-7
2.4.4
Reset, Stop, Mode Select, and Interrupt Timing
Table 2-7.
Reset, Stop, Mode Select, and Interrupt Timing6
No.
Characteristics
Expression
150 MHz
Unit
Min
Max
8
Delay from RESET assertion to all pins at reset value
3
——
26.0
ns
9
Required RESET duration4
Power on, external clock generator, PLL disabled
Power on, external clock generator, PLL enabled
Power on, internal oscillator
During STOP, XTAL disabled (PCTL Bit 16 = 0)
During STOP, XTAL enabled (PCTL Bit 16 = 1)
During normal operation
Minimum:
50
× ETC
1000
× ET
C
75000
× ETC
75000
× ETC
2.5
× T
C
2.5
× TC
333.3
6.67
0.50
16.7
—
ns
s
ms
ns
10
Delay from asynchronous RESET deassertion to first external address
output (internal reset deassertion)5
Minimum
Maximum
3.25
× TC + 2.0
20.25
× T
C + 10
23.7
—
145.0
ns
13
Mode select set-up time
30.0
—
ns
14
Mode select hold time
0.0
—
ns
15
Minimum edge-triggered interrupt request assertion width
6.6
—
ns
16
Minimum edge-triggered interrupt request deassertion width
6.6
—
ns
17
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external
memory access address out valid
Caused by first interrupt instruction fetch
Caused by first interrupt instruction execution
Minimum:
4.25
× T
C + 2.0
7.25
× TC + 2.0
30.4
51.0
—
ns
18
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-
purpose transfer output valid caused by first interrupt instruction
execution
Minimum:
10
× TC + 5.0
72.0
—
ns
19
Delay from address output valid caused by first interrupt instruction
execute to interrupt request deassertion for level sensitive fast
interrupts1, 7, 8
Maximum:
(WS + 3.75)
× TC – 10.94
—
Note 8
ns
20
Delay from RD assertion to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
Maximum:
(WS + 3.25)
× T
C – 10.94
—
Note 8
ns
21
Delay from WR assertion to interrupt request deassertion for level
sensitive fast interrupts1, 7, 8
DRAM for all WS
SRAM WS = 1
SRAM WS = 2, 3
SRAM WS
≥ 4
Maximum:
(WS + 3.5)
× TC – 10.94
(WS + 3.5)
× TC – 10.94
(WS + 3)
× T
C – 10.94
(WS + 2.5)
× TC – 10.94
—
Note 8
ns
24
Duration for IRQA assertion to recover from Stop state
5.9
—
ns
25
Delay from IRQA assertion to fetch of first instruction (when exiting
Stop)2, 3
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is
enabled
(Operating Mode Register Bit 6 = 0)
PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is
not enabled (Operating Mode Register Bit 6 = 1)
PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop
Delay)
PLC
× ETC × PDF + (128 K
PLC/2)
× TC
PLC
× ETC × PDF + (23.75 ±
0.5)
× TC
(8.25
± 0.5) × T
C
1.3
232.5 ns
51.7
9.1
12.3 ms
58.3
ms
ns
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