參數(shù)資料
型號(hào): DS87C530
廠商: Maxim Integrated Products, Inc.
英文描述: EPROM/ROM Micro with Real Time Clock(帶實(shí)時(shí)時(shí)鐘的EPROM/ROM高速微控制器)
中文描述: EPROM微控制器,帶有實(shí)時(shí)時(shí)鐘
文件頁數(shù): 6/41頁
文件大小: 437K
代理商: DS87C530
DS87C530/DS83C530
070898 6/41
PLCC
DESCRIPTION
SIGNAL
NAME
TQFP
27, 28
20, 21
RTCX2,
RTCX1
RTCX2, RTCX1 – Timekeeping crystal
. A 32.768 KHz crystal between these
pins supplies the time–base for the real time clock. The device supports both
6 pF and 12.5 pF load capacitance crystals as selected by an SFR bit described
below. To prevent noise from affecting the RTC, the RTCX2 and RTCX1 pin
should be guard–ringed with GND2.
2, 11,
13, 14,
40, 41
4, 6, 7,
33, 34,
47
NC
NC – Reserved.
These pins should not be connected. They are reserved for
use with future devices in the family.
COMPATIBILITY
The DS87C530/DS83C530 is a fully static CMOS 8051
compatible microcontroller designed for high perfor-
mance. While remaining familiar to 8051 users, it has
many new features. In general, software written for
existing 8051 based systems works without modifica-
tion on the DS87C530/DS83C530. The exception is
critical timing since the High Speed Micro performs its
instructions much faster than the original for any given
crystal selection. The DS87C530/DS83C530 runs the
standard 8051 instruction set. It is not pin compatible
with other 8051s due to the timekeeping crystal.
The DS87C530/DS83C530 provides three 16–bit timer/
counters, full–duplex serial port (2), 256 bytes of direct
RAM plus 1KB of extra MOVX RAM. I/O ports have the
same operation as a standard 8051 product. Timers will
default to a 12 clock per cycle operation to keep their
timing compatible with original 8051 systems. However,
timers are individually programmable to run at the new 4
clocks per cycle if desired. The PCA is not supported.
The DS87C530/DS83C530 provides several new hard-
ware features implemented by new Special Function
Registers. A summary of these SFRs is provided below.
PERFORMANCE OVERVIEW
The DS87C530/DS83C530 features a high speed 8051
compatible core. Higher speed comes not just from
increasing the clock frequency, but from a newer, more
efficient design.
This updated core does not have the dummy memory
cycles that are present in a standard 8051. A conven-
tional 8051 generates machine cycles using the clock
frequency divided by 12. In the DS87C530/DS83C530,
the same machine cycle takes four clocks. Thus the
fastest instruction, 1 machine cycle, executes three
times faster for the same crystal frequency. Note that
these are identical instructions. The majority of instruc-
tions on the DS87C530/DS83C530 will see the full 3 to
1 speed improvement. Some instructions will get
between 1.5 and 2.4 to 1 improvement. All instructions
are faster than the original 8051.
The numerical average of all opcodes gives approxi-
mately a 2.5 to 1 speed improvement. Improvement of
individual programs will depend on the actual instruc-
tions used. Speed sensitive applications would make
the most use of instructions that are three times faster.
However, the sheer number of 3 to 1 improved opcodes
makes dramatic speed improvements likely for any
code. These architecture improvements produce a
peak instruction cycle in 121 ns (8.25 MIPs). The Dual
Data Pointer feature also allows the user to eliminate
wasted instructions when moving blocks of memory.
INSTRUCTION SET SUMMARY
All instructions perform the same functions as their 8051
counterparts. Their effect on bits, flags, and other status
functions is identical. However, the timing of each
instruction is different. This applies both in absolute and
relative number of clocks.
For absolute timing of real–time events, the timing of
software loops can be calculated using a table in the
High–Speed Microcontroller User’s Guide. However,
counter/timers default to run at the older 12 clocks per
increment. In this way, timer–based events occur at the
standard intervals with software executing at higher
speed. Timers optionally can run at 4 clocks per incre-
ment to take advantage of faster processor operation.
The relative time of two instructions might be different in
the new architecture than it was previously. For exam-
ple, in the original architecture, the “MOVX A, @DPTR”
instruction and the “MOV direct, direct” instruction used
two machine cycles or 24 oscillator cycles. Therefore,
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