
DS87C530/DS83C530
070898 4/41
PIN DESCRIPTION
Table 1
PLCC
TQFP
SIGNAL
NAME
DESCRIPTION
52
45
V
CC
V
CC
– +5V
. Processor power supply.
1,25
18, 46
GND
GND
– Processor digital circuit ground.
29
22
V
CC2
V
– +5V Real Time Clock supply. V
CC2
is isolated from V
CC
to isolate the
RTC from digital noise.
26
19
GND2
GND2
– Real Time Clock circuit ground.
12
5
RST
RST – Input
. This pin contains a Schmitt voltage input to recognize external
active high Reset inputs. The pin also employs an internal pull–down resistor
to allow for a combination of wired OR external Reset sources. An RC is not
required for power–up, as the device provides this function internally.
23
24
16
17
XTAL2
XTAL1
XTAL1, XTAL2
– The crystal oscillator pins provide support for parallel reso-
nant, AT cut crystals. XTAL1 acts also as an input if there is an external clock
source in place of a crystal. XTAL2 is the output of the crystal amplifier.
38
31
PSEN
PSEN – Output
. The Program Store Enable output. This signal is a chip en-
able for optional external ROM memory. PSEN will provide an active low pulse
and is driven high when external ROM is not being accessed.
39
32
ALE
ALE – Output
. The Address Latch Enable output latches the external address
LSB from the multiplexed address/data bus on Port 0. This signal is commonly
connected to the latch enable of an external 373 family transparent latch. ALE
has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE
is forced high when the device is in a Reset condition. ALE can be disabled and
forced high by writing ALEOFF=1 (PMR.2). ALE operates independently of
ALEOFF during external memory accesses.
50
49
48
47
46
45
44
43
43
42
41
40
39
38
37
36
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
Port 0 (AD0–7) – I/O
. Port 0 is an open–drain 8–bit bi–directional I/O port. As
an alternate function Port 0 can function as the multiplexed address/data bus
to access off–chip memory. During the time when ALE is high, the LSB of a
memory address is presented. When ALE falls to a logic 0, the port transitions
to a bi–directional data bus. This bus is used to read external ROM and read/
write external RAM memory or peripherals. When used as a memory bus, the
port provides active high drivers. The reset condition of Port 0 is tri–state.
Pull–up resistors are required when using Port 0 as an I/O port.
3–10
48–52,
1–3
P1.0 – P1.7
Port 1 – I/O
. Port 1 functions as both an 8–bit bi–directional I/O port and an
alternate functional interface for Timer 2 I/O, new External Interrupts, and new
Serial Port 1. The reset condition of Port 1 is with all bits at a logic 1. In this state,
a weak pull–up holds the port high. This condition also serves as an input
mode, since any external circuit that writes to the port will overcome the weak
pull–up. When software writes a 0 to any port pin, the device will activate a
strong pull–down that remains on until either a 1 is written or a reset occurs.
Writing a 1 after the port has been at 0 will cause a strong transition driver to
turn on, followed by a weaker sustaining pull–up. Once the momentary strong
driver turns off, the port again becomes the output high (and input) state. The
alternate modes of Port 1 are outlined as follows.