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參數(shù)資料
| 型號： | DS87C530 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | EPROM/ROM Micro with Real Time Clock(帶實時時鐘的EPROM/ROM高速微控制器) |
| 中文描述： | EPROM微控制器，帶有實時時鐘 |
| 文件頁數(shù)： | 20/41頁 |
| 文件大小： | 437K |
| 代理商： | DS87C530 |
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DS87C530/DS83C530
070898 20/41
IDLE MODE
Setting the lsb of the Power Control register (PCON; 87h)
invokes the Idle mode. Idle will leave internal clocks,
serial ports and timers running. Power consumption
drops because the CPU is not active. Since clocks are
running, the Idle power consumption is a function of crys-
tal frequency. It should be approximately 1/2 of the opera-
tional power at a given frequency. The CPU can exit the
Idle state with any interrupt or a reset. Idle is available for
backward software compatibility. The system can now
reduce power consumption to below Idle levels by using
PMM1 or PMM2 and running NOPs.
STOP MODE ENHANCEMENTS
Setting bit 1 of the Power Control register (PCON; 87h)
invokes the Stop mode. Stop mode is the lowest power
state since it turns off all internal clocking. The I
CC
of a
standard Stop mode is approximately 1
μ
A but is speci-
fied in the Electrical Specifications. The CPU will exit
Stop mode from an external interrupt or a reset condi-
tion. Internally generated interrupts (timer, serial port,
watchdog) are not useful since they require clocking
activity. One exception is that a real time clock interrupt
can cause the device to exit Stop mode. This provides a
very power efficient way of performing infrequent yet
periodic tasks.
The DS87C530/DS83C530 provides two enhance-
ments to the Stop mode. As documented below, the de-
vice provides a band–gap reference to determine Pow-
er–fail Interrupt and Reset thresholds. The default state
is that the band–gap reference is off while in Stop mode.
This allows the extremely low power state mentioned
above. A user can optionally choose to have the band–
gap enabled during Stop mode. With the band–gap ref-
erence enabled, PFI and Power–fail reset are func-
tional and are a valid means for leaving Stop mode. This
allows software to detect and compensate for a brown–
out or power supply sag, even when in Stop mode.
In Stop mode with the band–gap enabled, I
CC
will be
approximately 50
μ
A compared with 1
μ
A with the
band–gap off. If a user does not require a Power–fail
Reset or Interrupt while in Stop mode, the band–gap
can remain disabled. Only the most power sensitive
applications should turn off the band–gap, as this
results in an uncontrolled power down condition.
The control of the band–gap reference is located in the
Extended Interrupt Flag register (EXIF; 91h). Setting
BGS (EXIF.0) to a 1 will keep the band–gap reference
enabled during Stop mode. The default or reset condi-
tion is with the bit at a logic 0. This results in the band–
gap being off during Stop mode. Note that this bit has no
control of the reference during full power, PMM, or Idle
modes.
The second feature allows an additional power saving
option while also making Stop easier to use. This is the
ability to start instantly when exiting Stop mode. It is the
internal ring oscillator that provides this feature. This
ring can be a clock source when exiting Stop mode in
response to an interrupt. The benefit of the ring oscilla-
tor is as follows.
Using Stop mode turns off the crystal oscillator and all
internal clocks to save power. This requires that the
oscillator be restarted when exiting Stop mode. Actual
start–up time is crystal dependent, but is normally at
least 4 ms. A common recommendation is 10 ms. In an
application that will wake–up, perform a short operation,
then return to sleep, the crystal start–up can be longer
than the real transaction. However, the ring oscillator
will start instantly. Running from the ring, the user can
perform a simple operation and return to sleep before
the crystal has even started. If a user selects the ring to
provide the start–up clock and the processor remains
running, hardware will automatically switch to the crys-
tal once a power–on reset interval (65536 clocks) has
expired. Hardware uses this value to assure proper
crystal start even though power is not being cycled.
The ring oscillator runs at approximately 2–4 MHz but
will not be a precise value. Do not conduct real–time
precision operations (including serial communication)
during this ring period. Figure 4 shows how the opera-
tion would compare when using the ring, and when
starting up normally. The default state is to exit Stop
mode without using the ring oscillator.
The RGSL – Ring Select bit at EXIF.1 (EXIF; 91h) con-
trols this function. When RGSL = 1, the CPU will use the
ring oscillator to exit Stop mode quickly. As mentioned
above, the processor will automatically switch from the
ring to the crystal after a delay of 65,536 crystal clocks.
For a 3.57 MHz crystal, this is approximately 18 ms. The
processor sets a flag called RGMD– Ring Mode,
located at EXIF.2, that tells software that the ring is
being used. The bit will be a logic 1 when the ring is in
use. Attempt no serial communication or precision tim-
ing while this bit is set, since the operating frequency is
not precise.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS87C530_05 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM/ROM Microcontrollers with Real-Time Clock |
| DS87C530_1 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM/ROM Micro with Real Time Clock |
| DS87C530+ECL | 制造商:Maxim Integrated Products 功能描述:MICRO OTP RTC 33MHZ 52P TQFP PB-FRR - Trays |
| DS87C530-ECL | 功能描述:8位微控制器 -MCU EPROM MCU w/RTC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| DS87C530-ECL+ | 功能描述:8位微控制器 -MCU EPROM MCU w/RTC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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