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參數(shù)資料
| 型號(hào)： | DS3134 |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 61/203頁 |
| 文件大?。?/td> | 777K |
| 代理商： | DS3134 |
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DS3134
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Bit 5 / VGA Control (VGA). This read only bit is forced to zero by the device to indicate that it is not a
VGA compatible device.
Bit 6 / Parity Error Response Control (PARC). This read/write bit controls whether or not the device
should ignore parity errors. When this bit is set to zero, the device will ignore any parity errors that it
detects and continue to operate normally. When this bit is set to one, the device must act on parity errors.
This bit is forced to zero when a hardware reset is initiated via the PRST* pin.
0 = ignore parity errors
1 = act on parity errors
Bit 7 / Address Stepping Control (STEPC). This read only bit is forced to zero by the device to indicate
that it is not capable of address/data stepping.
Bit 8 / PCI System Error Control (PSEC). This read/write bit controls whether or not the device
should enable the PSERR* output pin. When this bit is set to zero, the device will disable the PSERR*
pin and when this bit is set to one, the device will enable the PSERR* pin. This bit is forced to zero when
a hardware reset is initiated via the PRST* pin.
0 = disable the PSERR* pin
1 = enable the PSERR* pin
Bit 9 / Fast Back-to-Back Master Enable (FBBEN). This read only bit is forced to zero by the device
to indicate that it is not capable of generating fast back-to-back transactions to different agents.
Bits 10 to 15 / Reserved. These read only bits are forced to zero by the device.
STATUS BITS
The upper word in the PCMD0 register is the Status portion, which report events as they occur. As
mentioned earlier, reads of the Status portion occur normally but writes are unique in that bits can only be
reset (i.e. forced to zero). This occurs when a one is written to a bit position. Writes with a zero to a bit
position have no affect. This allows individual bits to be reset.
Bits 16 to 20 / Reserved. These read only bits are forced to zero by the device.
Bit 21 / 66 MHz Capable (66 MHz). This read only bit is forced to zero by the device to indicate that it
is not capable of running at 66 MHz.
Bit 22 / User Definable Features Capable (UDF). This read only bit is forced to zero by the device to
indicate that it does not support User Definable Features.
Bit 23 / Fast Back-to-Back Capable Target (FBBCT). This read only bit is forced to one by the device
to indicate that it is capable of accepting fast back-to-back transactions when the transactions are not from
the same agent.
Bit 24 / PCI Parity Error Reported (PARR). This read/write bit will be set to a one when the device is
a bus master and detects or asserts the PPERR* signal when the PARC command bit is enabled. This bit
can be reset (set to zero) by the Host by writing a one to this bit.
0 = no parity errors have been detected
1 = parity errors detected
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| DS3150TN | DATACOM, PCM TRANSCEIVER, PDIP48 |
| DS3150T | DATACOM, PCM TRANSCEIVER, PQFP48 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DS-313PIN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog Miscellaneous |
| DS-313-PIN | 功能描述:信號(hào)調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS31400 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter |
| DS31400DK | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 DS31400 Dev Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| DS31400GN | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Not Available From Mouser RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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