參數(shù)資料
型號(hào): DS3134
廠商: DALLAS SEMICONDUCTOR
元件分類(lèi): Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁(yè)數(shù): 32/203頁(yè)
文件大小: 777K
代理商: DS3134
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DS3134
127 of 203
DMA UPDATES TO THE DONE QUEUE
The Host has two options as to when the transmit DMA should write descriptors that have completed
transmission to the Done Queue. On a channel-by-channel basis, via the Done Queue Select (DQS) bit in
the Transmit DMA Configuration RAM, the Host can condition the DMA to:
1. Write to the Done Queue only when the complete HDLC packet has been transmitted (DQS = 0)
2. Write to the Done Queue when each data buffer has been transmitted (DQS = 1)
The Status field in the Done Queue Descriptor will be configured based on the setting of the DQS bit. If
DQS = 0, then when a packet has successfully completed transmission the Status field will be set to 000.
If DQS = 1, then when the first data buffer has successfully completed transmission the Status field will
be set to 001. When each middle buffer (i.e. the second through the next to last) has successfully
completed transmission the Status field will be set to 010. When the last data buffer of a packet has
successfully completed transmission, the Status field will be set to 011.
ERROR CONDITIONS
While processing packets for transmission, the DMA can encounter a number of error conditions, which
include;
- PCI error (an abort )
- Transmit FIFO underflow
- Channel is disabled (CHEN = 0) in the Transmit DMA Configuration RAM
- Channel number discrepancy between the Pending Queue & the Packet Descriptor
- Byte count of 0 bytes in the Packet Descriptor.
If any of these errors occur, the transmit DMA will automatically disable the affected channel by setting
the Channel Enable (CHEN) bit in the Transmit DMA Configuration RAM to zero and then it will write
the current descriptor into the Done Queue with the appropriate error status as shown in Table 8.2.1B
below.
Done Queue Error Status Conditions Table 8.2.1B
Packet
Status
Description of the Error
100
software provisioning error; this channel was not enabled
101
descriptor error; either byte count = 0 or channel code inconsistent with
Pending Queue
110
PCI error; abort
111
transmit FIFO error; it has underflowed
Since the transmit DMA has disabled the channel, any remaining queued descriptors will not be
transmitted and will be written to the Done Queue with a Packet Status of 100 (i.e. reporting that the
channel was not enabled). At this point, the Host has two options. Option 1, it can wait until all of the
remaining queued descriptors are written to the Done Queue with an errored status and then manually re-
enable the channel by setting the CHEN bit to one and then re-queue all of the affected packets. Option 2,
as soon as it detects an errored status, it can force the channel active again by setting the Channel Reset
(CHRST) bit to a one for the next descriptor that it writes to the Pending Queue for the affected channel.
As soon as the transmit DMA detects that the CHRST is set to a one, it will re-enable the channel by
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