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參數(shù)資料
| 型號： | DS3112+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 124/133頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX TEMPE T3/E3 256-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 控制器類型： | 調(diào)幀器，多路復(fù)用器 |
| 接口： | 并行/串行 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 150mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（27x27） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1419 (CN2011-ZH PDF) |
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DS3112
90 of 133
Register Name:
RHDLC
Register Description:
Receive HDLC FIFO
Register Address:
82h
Bit #
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
—
Bit #
15
14
13
12
11
10
9
8
Name
—
PS1
PS0
CBYTE
OBYTE
Default
—
Note 1: When the CPU bus is operated in the 8-bit mode (CMS = 1), the host should always read the lower byte (bits 0 to 7) first followed by
the upper byte (bits 8 to 15). Bits that are underlined are read-only; all other bits are read-write.
Note 2: Packets with three or fewer bytes (including the CRC FCS) in between flags are invalid and the data that appears in the FIFO in
such instances is meaningless. If only one byte is received between flags, then both the CBYTE and OBYTE bits will be set. If two bytes are
received, then OBYTE will be set for the first one received and CBYTE will be set for the second byte received. If three bytes are received,
then OBYTE will be set for the first one received and CBYTE will be set for the third byte received. In all of these cases, the packet status
will be reported as PS0 = 0/PS1 = 1 and the data in the FIFO should be ignored.
Bits 0 to 7: Receive FIFO Data (D0 to D7). Data from the Receive FIFO can be read from these bits. D0 is the
LSB and is received first while D7 is the MSB and is received last.
Bit 8: Opening Byte (OBYTE). This bit will be set to a one when the byte available at the D0 to D7 bits from the
Receive FIFO is the first byte of a HDLC packet.
Bit 9: Closing Byte (CBYTE). This bit will be set to a one when the byte available at the D0 to D7 bits from the
Receive FIFO is the last byte of a HDLC packet whether the packet is valid or not. The host can use the PS0 and
PS1 bits to determine if the packet is valid or not.
Bits 10 and 11: Packet Status Bits 0 and 1 (PS0 and PS1). These bits are only valid when the CBYTE bit is set
to a one. These bits inform the host of the validity of the incoming packet and the cause of the problem if the
packet was received in error.
PS1
PS0
PACKET
STATUS
REASON FOR INVALID RECEPTION OF THE PACKET
0
Valid
—
0
1
Invalid
Corrupt CRC
1
0
Invalid
Incoming packet was either too short (three or fewer bytes including the CRC) or
did not contain an integral number of octets
1
Invalid
Abort sequence detected
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112D1 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112D1+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112DK | 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
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