參數(shù)資料
型號： DS3112+
廠商： Maxim Integrated Products
文件頁數(shù)： 118/133頁
文件大?。?/td> 0K
描述： IC MUX TEMPE T3/E3 256-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 40
控制器類型： 調(diào)幀器，多路復(fù)用器
接口： 并行/串行
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 150mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-PBGA（27x27）
包裝： 管件
產(chǎn)品目錄頁面： 1419 (CN2011-ZH PDF)
DS3112
85 of 133
Register Name:
BERTEC0
Register Description:
BERT 24-Bit Error Counter (lower) and Status Information
Register Address:
7Ch
Bit #
7
6
5
4
3
2
1
0
Name
—
RA1
RA0
RLOS
BED
BBCO
BECO
SYNC
Default
—
Bit #
15
14
13
12
11
10
9
8
Name
BEC7
BEC6
BEC5
BEC4
BEC3
BEC2
BEC1
BEC0
Default
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Real-Time Synchronization Status (SYNC). Read-only real-time status of the synchronizer (this bit is not
latched). Will be set when the incoming pattern matches for 32 consecutive bit positions. Will be cleared when six
or more bits out of 64 are received in error.
Bit 1: BERT Error Counter Overflow (BECO). A latched read-only event-status bit that is set when the 24-bit
BERT Error Counter (BEC) saturates. Cleared when read and will not be set again until another overflow occurs
(i.e., the BEC counter must be cleared and allowed to overflow again). The setting of this status bit can cause a
hardware interrupt to occur if the IEOF bit in BERT Control Register 0 is set to a one and the BERT bit in the
Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read
(Figure 8-1).
Bit 2: BERT Bit Counter Overflow (BBCO). A latched read-only event-status bit that is set when the 32-bit
BERT Bit Counter (BBC) saturates. Cleared when read and will not be set again until another overflow occurs (i.e.,
the BBC counter must be cleared and allowed to overflow again). The setting of this status bit can cause a
hardware interrupt to occur if the IEOF bit in BERT Control Register 0 is set to a one and the BERT bit in the
Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read
(Figure 8-1).
Bit 3: Bit Error Detected (BED). A latched read-only event status bit that is set when a bit error is detected. The
receive BERT must be in synchronization for it to detect bit errors. This bit will be cleared when read. The setting
of this status bit can cause a hardware interrupt to occur if the IEBED bit in BERT Control Register 0 is set to a one
and the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to
clear when this bit is read (Figure 8-1).
Bit 4: Receive Loss Of Synchronization (RLOS). A latched read-only alarm-status bit that is set whenever the
receive BERT begins searching for a pattern. Once synchronization is achieved, this bit will remain set until read.
A change in this status bit (i.e., the synchronizer goes into or out of synchronization) can cause a hardware interrupt
to occur if the IESYNC bit in BERT Control Register 0 is set to a one and the BERT bit in the Interrupt Mask for
MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read (Figure 8-1).
Bit 5: Receive All Zeros (RA0). A latched read-only alarm-status bit that is set when 31 consecutive zeros are
received. Allowed to be cleared once a one is received.
Bit 6: Receive All Ones (RA1). A latched read-only alarm-status bit that is set when 31 consecutive ones are
received. Allowed to be cleared once a zero is received.
Bits 8 to 15: BERT 24-Bit Error Counter (BEC0 to BEC7). Lower byte of the 24-bit counter. See the
BERTEC1 register description for details.
相關(guān)PDF資料
PDF描述
PIC16F1847-E/P MCU 14KB FLASH 1KB RAM 18PDIP
DS21Q43AT+ IC FRAMER E1 QUAD 5V IND 128TQFP
PIC16LF1847-E/P MCU 14KB FLASH 1KB RAM 18PDIP
DS21Q43AT IC FRAMER E1 QUAD 5V IND 128TQFP
DS2143Q IC CONTROLLER E1 5V LP 44-PLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3112+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112DK 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*