參數(shù)資料
型號(hào): DS26303L-75
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 數(shù)字傳輸電路
英文描述: 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
中文描述: DATACOM, PCM TRANSCEIVER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, MS-026, LQFP-144
文件頁(yè)數(shù): 67/97頁(yè)
文件大?。?/td> 966K
代理商: DS26303L-75
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
67 of 97
After configuring these bits, the pattern must be loaded into the BERT. This is accomplished through a 0-to-1
transition on
BCR
.TNPL and
BCR
.RNPL
Monitoring the BERT requires reading the
BSR
register that contains the BEC bit and the OOS bit. The BEC bit is 1
when the bit-error counter is 1 or more. The OOS is 1 when the receive pattern generator is not synchronized to
the incoming pattern, which will occur when it receives a minimum 6 bit errors within a 64-bit window. The receive
BERT bit-count register (
RBCR
) and the receive BERT bit-error count register (
RBECR
) are updated upon the
reception of a performance-monitor update signal (e.g.,
BCR.
LPMU). This signal updates the registers with the
values of the counters since the last update and resets the counters.
6.9.2 Receive Pattern Detection
The receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming
pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or
bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating
polynomial x
+ x
+ 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is
bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator is
the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output is forced to 1 if the
next 14 bits are all 0s. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback is forced to
1 if bits 1 through 31 are all 0s. Depending on the type of pattern programmed, pattern detection performs either
PRBS synchronization or repetitive pattern synchronization.
6.9.2.1
Receive PRBS Synchronization
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If
at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern
re-synchronization is initiated. Automatic pattern resynchronization can be disabled.
Refer to
Figure 6-11
for the PRBS synchronization diagram.
Figure 6-11. PRBS Synchronization State Diagram
Sync
Load
Verify
1 bit error
32 bits loaded
3 i ihueos
6o6 i ihros
相關(guān)PDF資料
PDF描述
DS26303LN-120 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
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DS26303L-75+ 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303L-75+A3 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303L-75A3 功能描述:電信線路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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