參數(shù)資料
型號(hào)： DS26303L-75
廠(chǎng)商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
中文描述： DATACOM, PCM TRANSCEIVER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, MS-026, LQFP-144
文件頁(yè)數(shù)： 63/97頁(yè)
文件大?。?/td> 966K
代理商： DS26303L-75
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
63 of 97
6.6 Jitter Attenuator
The DS26303 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits by the JADS
bit in register
GC.
It can also be controlled on an individual LIU basis by settings in the
IJAFDS
register. The 128-
bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay-
sensitive applications. The characteristics of the attenuation are shown in
Figure 6-7
. The jitter attenuator can be
placed in either the receive path or the transmit path or none by appropriately setting the JAPS and the JAE bits in
register
GC
. These selections can be changed on an individual LIU basis by settings in the
IJAPS
and
IJAE
.
For the jitter attenuator to properly operate, a 2.048MHz or multiple thereof, or 1.544MHz clock or multiple thereof
must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1
applications. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. On-board circuitry adjusts
either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin to create a
smooth jitter-free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a
gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming jitter
exceeds either 120UI
P-P
(buffer depth is 128 bits) or 28UI
P-P
(buffer depth is 32 bits), then the DS26303 divides the
internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17 instead of the normal 16 to keep the
buffer from overflowing. When the device divides by either 15 or 17, it also sets the jitter attenuator limit trip (JFLT)
bits in the
IJAFLT
register described.
Figure 6-7. Jitter Attenuation
FREQUENCY (Hz)
0dB
-20dB
-40dB
-60dB
1
10
100
1K
10K
J
100K
TR 62411 (Dec. 90)
Prohibited Area
CreB
CuveA
ITU G.7XX
Prohibited Area
TBR12
Prohibited
Area
T1
E1
相關(guān)PDF資料
PDF描述
DS26303LN-120 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303LN-75 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
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DS26518G 8-Port T1/E1/J1 Transceiver
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26303L-75+ 功能描述:電信線(xiàn)路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303L-75+A3 功能描述:電信線(xiàn)路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303L-75A3 功能描述:電信線(xiàn)路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303LN-120 功能描述:電信線(xiàn)路管理 IC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
DS26303LN-120+ 功能描述:電信線(xiàn)路管理 IC 3.3V E1/T1/J1 Short Haul Octal LIU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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