參數(shù)資料
型號(hào): DS2151Q
英文描述: T1 Single-Chip Transceiver
中文描述: T1單芯片收發(fā)器
文件頁(yè)數(shù): 40/51頁(yè)
文件大?。?/td> 1100K
代理商: DS2151Q
DS2151Q
40 of 51
2.048 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED
Figure 13-5
NOTES:
1.
RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to 1; TSER ignored during these
channels.
2.
RSYNC is in the output mode (RCR2.3=0).
3.
RSYNC is in the input mode (RCR2.3=1).
4.
RCHBLK is forced to 1 in the same channels as RSER (see Note 1).
TRANSMIT SIDE D4 TIMING
Figure 13-6
NOTES:
1.
TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is not enabled (TCR2.4=0).
2.
TSYNC in the frame mode (TCR2.3=0) and double-wide frame sync is enabled (TCR2.4=1).
3.
TSYNC in the multiframe mode (TCR2.3=1).
4.
TLINK data (S-bit) is sampled during the F-bit position of even frames for insertion into the outgoing
T1 stream when enabled via TCR1.2.
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