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參數(shù)資料
| 型號： | DS2151Q |
| 英文描述： | T1 Single-Chip Transceiver |
| 中文描述： | T1單芯片收發(fā)器 |
| 文件頁數(shù)： | 26/51頁 |
| 文件大?。?/td> | 1100K |
| 代理商： | DS2151Q |
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DS2151Q
26 of 51
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers
(RFDLM1/RFDLM2), SR2.2 will be set to a 1 and the
INT2
will go active if enabled via IMR2.2.
6.2 Transmit Section
The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or
the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value
is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing
T1 data stream. After the full 8 bits have been shifted out, the DS2151Q will signal the host
microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a 1. The
INT2
will also toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new
value. If the TFDL is not updated, the old value in the TFDL will be transmitted once again.
The DS2151Q also contains a 0 stuffer which is controlled via the CCR2.4 bit. In both ANSI T1.403 and
TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states
that no more than five 1s should be transmitted in a row so that the data does not resemble an opening or
closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the DS2151Q will
automatically look for five 1s in a row. If it finds such a pattern, it will automatically insert a 0 after the
five 1s. The CCR2.4 bit should always be set to a 1 when the DS2151Q is inserting the FDL. More on
how to use the DS2151Q in FDL and SLC-96 applications is covered in a separate Application Note.
TFDL: TRANSMIT FDL REGISTER
(Address=7E Hex)
(MSB)
TFDL7
TFDL6
TFDL5
(LSB)
TFDL0
TFDL4
TFDL3
TFDL2
TFDL1
SYMBOL
TFDL7
POSITION
TFDL.7
NAME AND DESCRIPTION
MSB of the FDL code to be transmitted
TFDL0
TFDL.0
LSB of the FDL code to be transmitted
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be
inserted on a byte basis into the outgoing T1 data stream in ESF mode. The LSB is transmitted first. In
D4 operation the TFDL can be the source of the Fs pattern. In this case a 1ch is written to the TFDL
register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2151 | T1 Single-Chip Transceiver |
| DS2154L | Enhanced E1 Single Chip Transceiver |
| DS2154LN | Enhanced E1 Single Chip Transceiver |
| DS2154 | WSD 151 SOLDERING STATION 230V UKWSD 151 SOLDERING STATION 230V UK; Frequency, supply max:60Hz; Frequency, supply min:50Hz; Height:101mm; Length:166mm; Power, input:150W; Temperature range:50(degree C) - 550(degree C); Voltage, |
| DS2155 | T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2151Q/T&R | 制造商:Maxim Integrated Products 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC |
| DS2151Q/T&R | 功能描述:IC TXRX T1 1-CHIP 5V LP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| DS2151QB | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2151QB/T&R | 制造商:Maxim Integrated Products 功能描述:T1 SINGLE CHIP XCVR REV B T&R - Tape and Reel |
| DS2151QB/T&R+ | 制造商:Maxim Integrated Products 功能描述:FRAMER DS1/E1/ISDN-PRI/T1 5V 44PLCC - Tape and Reel |
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