參數(shù)資料
型號: DS2151Q
英文描述: T1 Single-Chip Transceiver
中文描述: T1單芯片收發(fā)器
文件頁數(shù): 38/51頁
文件大?。?/td> 1100K
代理商: DS2151Q
DS2151Q
38 of 51
RECEIVE SIDE ESF TIMING
Figure 13-2
NOTES:
1.
RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is not enabled (RCR2.5=0).
2.
RSYNC in the frame mode (RCR2.4=0) and double-wide frame sync is enabled (RCR2.5=1).
3.
RSYNC in the multiframe mode (RCR2.4=1).
4.
ZBTSI mode disabled (RCR2.6=0).
5.
RLINK data (FDL bits) is updated 1 bit-time before odd frames and held for two frames.
6.
ZBTSI mode is enabled (RCR2.6=1).
7.
RLINK data (Z bits) is updated 1 bit-time before odd frame and held for four frames.
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