參數(shù)資料
型號(hào): DM9102D
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP FAST ETHEMET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)NIC控制器
文件頁(yè)數(shù): 50/70頁(yè)
文件大小: 2245K
代理商: DM9102D
50
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
7.4 Serial Management Interface
The serial management interface is used to obtain and
control the status of PHY management register set through
the internal MDC and MDIO signals, which is control by
CR9 bits 19:16. The Management Data Clock (MDC) is
equipped with a maximum clock rate of 2.5MHz.
In read/write operation, the management data frame is
64-bit long start with 32 contiguous logic one bits (preamble)
synchronization clock cycles on MDC. The Start of Frame
Delimiter (SFD) is indicated by a <01> pattern followed by
7.4.1 Management Interface - Read Frame Structure
the operation code (OP):<10> indicates Read operation and
<01> indicates Write operation. Following the OP Code is
the 5-bit PHY Address field that is fixed to 00001b. For read
operation, a 2-bit turnaround (TA) filing between Register
Address field and Data field is provided for MDIO to avoid
contention. “Z” stands for the state of high impedance.
Following turnaround time, a 16-bit data is read from or
written onto management registers.
32 "1"s
0
1
1
0
A4
A3
A0
R4
R3
R0
Z
0
Idle
Preamble
SFD
Op Code
PHY Address
Register Address
Turn Around
Data
Read
Idle
Write
MDC
MDIO Read
D15
D14
D1
D0
//
//
7.4.2 Management Interface - Write Frame Structure
32 "1"s
0
1
1
0
A4
A3
A0
R4
R3
R0
1
0
D15
D14
D1
D0
Idle
Preamble
SFD
Op Code
PHY Address
Register Address
Write
Turn Around
Data
Idle
MDC
MDIO Write
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