參數(shù)資料
型號(hào): DM9102D
廠商: Electronic Theatre Controls, Inc.
英文描述: SINGLE CHIP FAST ETHEMET NIC CONTROLLER
中文描述: 單晶片快速以太網(wǎng)NIC控制器
文件頁(yè)數(shù): 39/70頁(yè)
文件大小: 2245K
代理商: DM9102D
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
39
b3 b2 b1 b0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
In DLE tate
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match ail
Parallel etects ignal_link_ready
Parallel etects ignal_link_ready
fail
Auto-negotiation ompleted
successfully
1
0
0
0
6.3.10 10BASE-T Configuration/Status (10BTCSRCSR) – 12H
Bit
Name
15
Reserved
Default
0, RO
Description
Reserved:
Write as 0, ignore on read
Link Pulse Enable:
1=Transmission of link pulses enabled
0=Link pulses disabled, good link condition forced
This bit is valid only in 10Mbps operation.
Heartbeat Enable:
1=Heartbeat function enabled
0=Heartbeat function disabled
When the DM9102D is configured for Full Duplex operation, this bit will be
ignored (the collision/heartbeat function is invalid in Full Duplex mode). It must
set to be 1.
Squelch Enable
1 = normal squelch
0 = low squelch
Jabber Enable:
Enables or disables the Jabber function when the DM9102D is in 10BASE-T
Full Duplex or 10BASE-T Transceiver Loopback mode
1= Jabber function enabled
0= Jabber function disabled
Reserved
Reserved
Reserved
Polarity Reversed
When this bit is set to 1, it indicates that the 10Mbps cable polarity is
reversed.
14
LP_EN
1, RW
13
HBE
1,RW
12
SQUELCH
1, RW
11
JABEN
1, RW
10
9:2
1
0
Reserved
Reserved
Reserved
POLR
0,RW
0, RO
1,RW
0, RO
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