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參數(shù)資料
| 型號(hào)： | DM9102D |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| 中文描述： | 單晶片快速以太網(wǎng)NIC控制器 |
| 文件頁數(shù)： | 25/70頁 |
| 文件大小： | 2245K |
| 代理商： | DM9102D |
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Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
25
Transmit process will be aborted and placed in the stop state. It also causes transmit
jabber timeout TDES0<14> to assert.
Transmit Buffer Unavailable
This bit is set when the DM9102D fetches the next transmit descriptor that is still
owned by the host. Transmit process will be suspended until the transmission polling
command is set.
Transmit Process Stopped
This bit is set to indicate transmit process enters the stopped state.
Transmit Complete Interrupt
This bit is set when a frame is fully transmitted and transmit status has been written to
descriptor (the TDES1<31> is also asserted). Transmit process is still running and
continues to fetch next descriptor.
2
TXDU
0,RW
1
TXPS
0,RW
0
TXCI
0,RW
6.2.7 Network Operation Mode Register (CR6)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
0
0
0
Bit
31
30
Name
Reserved
RXA
Default
0,RO
0,RW
Description
Must be Zero
Receive All
When set, all incoming packet will be received, regardless the destination address.
The address match is checked according to theCR6<7>, CR6<6>, CR6<4>,
CR6<2>, CR6<0>, and RDES0<30> will show this match
Set to not purge RX FIFO for test only if RX buffer unavailable.
Must be Zero
Must be One
Must be Zero
Transmit Threshold Mode
When set, the transmit threshold mode is 10Mb/s. When reset, the threshold mode
is 100Mb/s. This bit is used together with CR6<15:14> to decide the exact
threshold level.
Store and Forward Transmit
When set, the packet transmission will be started after a full frame has been moved
from the host memory to transmit FIFO. When reset, the packet transmission’s start
will depend on the threshold value specified in CR6<15:14>.
Reserved
Reserved
In external MII mode, use this bit to enable or disable internal PHY
See page 56 “7.8 External MII Interface” for details.
Reserved
One Packet Mode
When this bit is set, only one packet is stored at TX FIFO
29
28:26
25
24:23
22
NPFIFO
Reserved
Reserved
Reserved
TXTM
0,RW
000,RO
1,RO
00,RO
1,RW
21
SFT
0,RW
20
19
18
Reserved
Reserved
External
MII_ Mode
Reserved
1PKT
0,RW
0,RW
1,RW
17
16
0,RO
0,RW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM9102DE | SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| DM9102 | Single Chip Fast Ethernet NIC controller |
| DM9102A | Single Chip Fast Ethernet NIC controller |
| DM9102AF | Single Chip Fast Ethernet NIC controller |
| DM9102AT | Single Chip Fast Ethernet NIC controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9102DE | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9102DEP | 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes |
| DM9102H | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9102HEP | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9103 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface |
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