Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
49
7.3 Network Function
7.3.1 Overview
This chapter will introduce the normal state machine
operation and MAC layer management like collision back-off
algorithm. In transmit mode, the DM9102D initiates a DMA
cycle to access data from a transmit buffer. It prefaces the
data with the preamble, the SFD pattern, and it appends a
32-bit CRC. In receive mode, the data is de-serialized by
receive mechanism and is fed into the internal FIFO. For
detailed process, please see below.
7.3.2 Receive Process and State Machine
a. Reception Initiation
As a preamble being detected on receive data lines, the
DM9102D synchronizes itself to the data stream during the
preamble and waits for the SFD. The synchronization
process is based on byte boundary and the SFD byte is
10101011. If the DM9102D receives a 00 or a 11 after the
first 8 preamble bits and before receiving the SFD, the
reception process will be terminated.
b. Address Recognition
After initial synchronization, the DM9102D will recognize the
6-byte destination address field. The first bit of the
destination address signifies whether it is a physical address
(=0) or a multicast address (=1). The DM9102D filters the
frame based on the node address of receive address filter
setting. If the frame passes the filter, the subsequent serial
data will be delivered into the host memory.
c. Frame Decapsulation
The DM9102D checks the CRC bytes of all received frames
before releasing the frame along with the CRC to the host
processor.
7.3.3 Transmit Process and State Machine
a. Transmission Initiation
Once the host processor prepares a transmit descriptor for
the transmit buffer, the host processor signals the DM9102D
to take it. After the DM9102D has been notified of this
transmit list, the DM9102D will start to move the data bytes
from the host memory to the internal transmit FIFO. When
the transmit FIFO is adequately filled to the programmed
threshold level, or when there is a full frame buffered into the
transmit FIFO, the DM9102D begins to encapsulate the
frame. The transmit encapsulation is performed by the
transmit state machine, which delays the actual
transmission onto the network until the network has been
idle for a minimum inter frame gap time.
b. Frame Encapsulation
The transmit data frame encapsulation stream consists of
two parts: Basic frame beginning and basic frame end. The
former contains 56 preamble bits and SFD, the later, FCS.
The basic frame read from the host memory includes the
destination address, the source address, the type/length
field, and the data field. If the data field is less than 46 bytes,
the DM9102D will pad the frame with pattern up to 46 bytes.
c. Collision
When concurrent transmissions from two or more nodes
occur (termed; collision), the DM9102D halts the
transmission of data bytes and begins a jam pattern
consisting of AAAAAAAA. At the end of the jam
transmission, it begins the backoff wait time. If the collision
was detected during the preamble transmission, the jam
pattern is transmitted after completing the preamble. The
backoff process is called truncated binary exponential
backoff. The delay is a random integer multiple of slot times.
The number of slot times of delay before the Nth
retransmission attempt is chosen as a uniformly distributed
random integer in the range:
0
≤
r < 2k
k = min ( n, N ) and N=10
7.3.4 Physical Layer Overview
The DM9102D supports 100Mbps and 10Mbps operation. It
provides a direct interface either to Unshielded Twisted Pair
cable UTP5 for 100BASE-TX fast Ethernet, or UTP5/UTP3
cable for 10BASE-T Ethernet. In physical level operation, it
consists of the following functions:
PCS: 4B5B encode/decode, scramble/de-scramble, and
data serialize/parallelize
NRZ/NRZI, MLT-3 encoder/decoder and driver
MANCHESTER encoder/decoder
10BASE-T filter, driver/receiver, and MANCHESTER
encoder/decoder
Auto. MDI/MDIX detection