參數(shù)資料
型號(hào)： DM9102D
廠商： Electronic Theatre Controls, Inc.
英文描述： SINGLE CHIP FAST ETHEMET NIC CONTROLLER
中文描述： 單晶片快速以太網(wǎng)NIC控制器
文件頁(yè)數(shù)： 26/70頁(yè)
文件大小： 2245K
代理商： DM9102D
26
Preliminary datasheet
Version: DM9102D-DS-P02
Jan. 14, 2005
15:14
TSB
0,RW
Threshold Bits
These bits are set together with CR6 [22] and will decide the exact FIFO threshold
level. The packet transmission will start after the data in the FIFO exceeds the
threshold value.
Bit 22 Bit15 Bit14 Threshold
0 0 0 128 bytes
0 0 1 256 bytes
0 1 0 512 bytes
0 1 1 1024 bytes
1 0 0 64 bytes
1 0 1 128 bytes
1 1 0 192 bytes
1 1 1 256 bytes
Transmit Start/Stop Command
When set, the transmit process will begin by fetching the transmit descriptor for
available packet data to be transmitted (running state). If the fetched descriptor is
owned by the host, transmit process will enter the suspend state and transmit buffer
unavailable (CR5<2>) is set. Otherwise it will begin to move data from host to
FIFO and transmit out after reaching threshold value.
When reset, the transmit process is placed in the stopped state after completing the
transmission of the current frame.
Force Collision Mode
When set, the transmission process is forced to be the collision status. Meaningful
only in the internal loop-back mode.
Loop-back Mode
These bits decide two loop-back modes, MAC and PHY, besides normal
operation. These loop-back modes expect transmitted data back to receive path
and ignore collision detection.
Bit11 Bit10 Loop-back Mode
0 0 Normal
0 1 Internal loop-back
1 0 Internal PHY digital loop-back
1 1 Internal PHY analog loop-back
Full-duplex Mode
When internal PHY is selected, this bit is the status of full-duplex mode of internal
PHY.
When external PHY is selected, set this bit to make the MAC of the DM9102D
operate in the full-duplex mode.
Must be Zero
Pass All Multicast
When set, any packet with a multicast destination address is received by the
DM9102D. The packet with a physical address will also be filtered based on the
filter mode setting
Promiscuous Mode
When set, any incoming valid frame is received by the DM9102D, and no matter
what the destination address is. The DM9102D is initialized to this mode after reset
operation.
Must be Zero
13
TXSC
0,RW
12
FCM
0,RW
11:10
LBM
0,RW
9
FDM
0,RW
8
7
Reserved
PAM
0,RO
0,RW
6
PM
0,RW
5
Reserved
0,RO
相關(guān)PDF資料
PDF描述
DM9102DE SINGLE CHIP FAST ETHEMET NIC CONTROLLER
DM9102 Single Chip Fast Ethernet NIC controller
DM9102A Single Chip Fast Ethernet NIC controller
DM9102AF Single Chip Fast Ethernet NIC controller
DM9102AT Single Chip Fast Ethernet NIC controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9102DE 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
DM9102DEP 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes
DM9102H 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
DM9102HEP 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
DM9103 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface
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