參數(shù)資料
型號(hào)： DM9000
廠商： Electronic Theatre Controls, Inc.
英文描述： ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY
中文描述： ISA以以太網(wǎng)MAC控制器，它集成10/100網(wǎng)卡芯片
文件頁(yè)數(shù)： 29/54頁(yè)
文件大?。?/td> 575K
代理商： DM9000
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
This bit is self-clear after reset is completed
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
0, RW
Sleep Mode
Writing a 1 to this bit will cause PHY to enter the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Remote Loopout Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
Final
Version: DM9000-DS-F02
June 26, 2002
29
16.2
MFPSC
0, RW
16.1
SLEEP
16.0
RLOUT
0, RW
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Bit
Bit Name
Default
17.15
100FDX
1, RO
Description
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M full duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M half duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 10M Full Duplex
mode. The software can read bit [15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 10M half duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
Reserved
Write as 0, ignore on read
PHY Address Bit 4:0
The first PHY address bit transmitted or received is the MSB of the
address (bit 4). A station management entity connected to multiple
PHY entities must know the appropriate address of each PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be
written to these bits
17.14
100HDX
1, RO
17.13
10FDX
1, RO
17.12
10HDX
1, RO
17.11-
17.9
17.8-17.4
RESERVED
0, RO
PHYADR[4:0]
(PHYADR),
RW
17.3-17.0
ANMB[3:0]
0, RO
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DM9000E ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9000()EVB 制造商:DAVICOM 功能描述:BOARD EVALUATION DM9000 制造商:DAVICOM 功能描述:DM9000, MAC CNTLR, ENET, EVAL BOARD 制造商:DAVICOM 功能描述:EVAL BOARD, DM9000, MAC CNTLR, ENET; ;ROHS COMPLIANT: YES
DM9000_09 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:ISA to Ethernet MAC Controller with Integrated 10/100 PHY
DM9000A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ethernet Controller with General Processor Interface 臺(tái)灣Davicom公司出品的48pin、10/100M網(wǎng)絡(luò)控制芯片
DM9000A_06 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface
DM9000AE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ethernet Controller with General Processor Interface
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