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參數(shù)資料
| 型號(hào)： | DM9000 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| 中文描述： | ISA以以太網(wǎng)MAC控制器，它集成10/100網(wǎng)卡芯片 |
| 文件頁數(shù)： | 20/54頁 |
| 文件大小： | 575K |
| 代理商： | DM9000 |
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
20
Final
Version: DM9000-DS-F02
June 26, 2002
6.30 Memory data write command with address increment Register (F8H)
Bit
Name
Default
7:0
MWCMD
X,WO
Description
Write Data to TX SRAM
After the write of this command, the write pointer is increased by 1,2, or 4, depends
on the operator mode. (8-bit, 16-bit,32-bit respectively)
6.31 Memory data write_address Register (FAH~FBH)
Bit
Name
Default
7:0
MDRAH
00H,R/W
7:0
MDRAL
00H,R/W
Description
Memory Data Write_ address High Byte
Memory Data Write_ address Low Byte
6.32 TX Packet Length Register (FCH~FDH)
Bit
Name
7:0
TXPLH
7:0
TXPLL
Default
X,R/W
X,,R/W
Description
TX Packet Length High byte
TX Packet Length Low byte
6.33 Interrupt Status Register (FEH)
Bit
Name
7:6
IOMODE
Default
0, RO
Description
Bit 7 Bit 6
0 0 16-bit mode
0 1 32-bit mode
1 0 8-bit mode
1 1 Reserved
Reserved
Receive Overflow Counter Overflow Latch
Rx Overflow Latch
Packet Transmitted Latch
Packet Received Latch
5~4
3
2
1
0
RESERVED
ROOS
ROS
PTS
PRS
0,RO
0,RW/C1
0,RW/C1
0,RW/C1
0,RW/C1
6.34 Interrupt Mask Register (FFH)
Bit
Name
7
PAR
Default
0,RW
Description
Enable the SRAM read/write pointer to automatically return to the start address
when pointer addresses are over the SRAM size. Driver needs to set. When driver
sets this bit, REG_F5 will set to 0Ch automatically
Reserved
Enable Receive Overflow Counter Overflow Latch
Enable RX Overflow Latch
Enable Packet Transmitted Latch
Enable Packet Received Latch
6~4
3
2
1
0
RESERVED
ROOM
ROM
PTM
PRM
0,RO
0,RW
0,RW
0,RW
0,RW
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM9000E | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| DM9006CJ | Gate Expander |
| DM9006CN | Gate Expander |
| DM9009CJ | Dual 4-input NAND Gate |
| DM9009CN | Dual 4-input NAND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9000()EVB | 制造商:DAVICOM 功能描述:BOARD EVALUATION DM9000 制造商:DAVICOM 功能描述:DM9000, MAC CNTLR, ENET, EVAL BOARD 制造商:DAVICOM 功能描述:EVAL BOARD, DM9000, MAC CNTLR, ENET; ;ROHS COMPLIANT: YES |
| DM9000_09 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:ISA to Ethernet MAC Controller with Integrated 10/100 PHY |
| DM9000A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ethernet Controller with General Processor Interface 臺(tái)灣Davicom公司出品的48pin、10/100M網(wǎng)絡(luò)控制芯片 |
| DM9000A_06 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface |
| DM9000AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ethernet Controller with General Processor Interface |
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