參數(shù)資料
型號(hào): DM9000
廠商: Electronic Theatre Controls, Inc.
英文描述: ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY
中文描述: ISA以以太網(wǎng)MAC控制器,它集成10/100網(wǎng)卡芯片
文件頁(yè)數(shù): 28/54頁(yè)
文件大?。?/td> 575K
代理商: DM9000
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
28
Final
Version: DM9000-DS-F02
June 26, 2002
NP_ABLE = 1: next page available
NP_ABLE = 0: no next page
New Page Received
A new link of code-word page received. This bit will be
automatically cleared when the register (register 6) is read by
management
Link Partner Auto-negotiation Able
A “1” in this bit indicates that the link partner supports Auto-
negotiation
6.1
PAGE_RX
0, RO/LH
6.0
LP_AN_ABLE
0, RO
8.8 DAVICOM Specified Configuration Register (DSCR) - 16
Bit
Bit Name
16.15
BP_4B5B
Default
0, RW
Description
Bypass 4B5B Encoding and 5B4B Decoding
1 = 4B5B encoder and 5B4B decoder function bypassed
0 = Normal 4B5ccccccccB and 5B4B operation
Bypass Scrambler/Descrambler Function
1 = Scrambler and descrambler function bypassed
0 = Normal scrambler and descrambler operation
Bypass Symbol Alignment Function
1 = Receive functions (descrambler, symbol alignment and symbol
decoding functions) bypassed. Transmit functions
(symbol encoder and scrambler) bypassed
0 = Normal operation
Bypass ADPOK
Force signal detector (SD) active. This register is for debug only,
not release to customers.
1=Force SD is OK
0=Normal operation
Reserved
Write as 0, ignore on read
100BASE-TX
1 = 100BASE-TX operation
0 = Reserved
Reserved
Reserved
Write as 0, ignore on read
Force Good Link in 100Mbps
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
Reserved
Write as 0, ignore on read
Reserved
Write as 0, ignore on read
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0: Disable automatic reduced power down
1: Enable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
16.14
BP_SCR
0, RW
16.13
BP_ALIGN
0, RW
16.12
BP_ADPOK
0, RW
16.11
RESERVED
0, RO
16.10
TX
1, RO
16.9
16.8
RESERVED
RESERVED
0, RO
0, RO
16.7
F_LINK_100
0, RW
16.6
RESERVED
0, RO
16.5
RESERVED
0, RO
16.4
RPDCTR-EN
1, RW
16.3
SMRST
0, RW
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