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參數(shù)資料
| 型號： | DM9000 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| 中文描述： | ISA以以太網(wǎng)MAC控制器，它集成10/100網(wǎng)卡芯片 |
| 文件頁數(shù)： | 25/54頁 |
| 文件大小： | 575K |
| 代理商： | DM9000 |
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final
Version: DM9000-DS-F02
June 26, 2002
25
operation)
0 = Link is not established
The link status bit is implemented with a latching function, so that the
occurrence of a link failure condition causes the link status bit to be,
and remain cleared until it is read via the management interface
Jabber Detect
1 = Jabber condition detected
0 = No jabber
This bit is implemented with a latching function. Jabber conditions
will set this bit unless it is cleared by a read to this register through a
management interface or a PHY reset. This bit works only in 10Mbps
mode
Extended Capability
1 = Extended register capable
0 = Basic register capable only
1.1
Jabber detect
0,
RO/LH
1.0
Extended
capability
1,RO/P
8.3 PHY ID Identifier Register #1 (PHYID1) - 02
The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9000. The Identifier consists
of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model number, and a model
revision number. DAVICOM Semiconductor's IEEE assigned OUI is 00606E
Bit
Bit Name
OUI_MSB
Default
<0181H>
Description
2.15-2.0
OUI Most Significant Bits
Bit 3 to 18 of the OUI (00606E) are mapped to bit 15 to 0 of this
register respectively. The most significant two bits of the OUI are
ignored (the IEEE standard refers to these as bit 1 and 2)
8.4 PHY Identifier Register #2 (PHYID2) - 03
Bit
Bit Name
3.15-3.10
OUI_LSB
Default
<101110>,
RO/P
Description
OUI Least Significant Bits
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this
register respectively
Vendor Model Number
Six bits of vendor model number mapped to bit 9 to 4 (most
significant bit to bit 9)
Model Revision Number
Four bits of vendor model revision number mapped to bit 3 to 0
(most significant bit to bit 3)
3.9-3.4
VNDR_MDL
<001100>,
RO/P
3.3-3.0
MDL_REV
<0000>,
RO/P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM9000E | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| DM9006CJ | Gate Expander |
| DM9006CN | Gate Expander |
| DM9009CJ | Dual 4-input NAND Gate |
| DM9009CN | Dual 4-input NAND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9000()EVB | 制造商:DAVICOM 功能描述:BOARD EVALUATION DM9000 制造商:DAVICOM 功能描述:DM9000, MAC CNTLR, ENET, EVAL BOARD 制造商:DAVICOM 功能描述:EVAL BOARD, DM9000, MAC CNTLR, ENET; ;ROHS COMPLIANT: YES |
| DM9000_09 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:ISA to Ethernet MAC Controller with Integrated 10/100 PHY |
| DM9000A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ethernet Controller with General Processor Interface 臺灣Davicom公司出品的48pin、10/100M網(wǎng)絡(luò)控制芯片 |
| DM9000A_06 | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Ethernet Controller with General Processor Interface |
| DM9000AE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Ethernet Controller with General Processor Interface |
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