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參數(shù)資料
| 型號： | D950-CORE |
| 廠商： | 意法半導體 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Fixed Point Digital Signal Processor DSP Core |
| 中文描述： | 16位定點數(shù)字信號處理器DSP核 |
| 文件頁數(shù)： | 79/89頁 |
| 文件大?。?/td> | 560K |
| 代理商： | D950-CORE |
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D950-Core
7.4.3 Operation
The DMA controller interface contains four independent channels allowing data transfer on I-
memory space and simultaneous data transfer on X and Y-memory spaces. When requests
occur at the same time on different channels, to transfer data on the same bus, the requests
are concatenated to be acknowledged during the same transfer, according to the following
fixed priority (see table):
The DMA transfer is based on a DSP cycle stealing operation:
The DMA controller generates a ‘hold request’ to the AS-DSP.
The AS-DSP sends back a ‘hold acknowledge’ to the DMA controller and
enters the hold state (bus released).
The DMA controller, manages the transfer and enters its idle state at the end of
the transfer, until reception of a new DMA request. The ‘hold request’ signal is
removed.
The data transfer duration is n+2 cycles, split into:
One cycle inserted at the beginning of the transfer when bus controls are
released by the D950-Core, n cycles for the number of data words to be trans-
ferred.
Another cycle is inserted at the end of the transfer when bus controls are
released by the DMA controller.
Single or block data can be transferred. The ‘DMA request’ signal is well adapted to such data
transfers by being either edge (single) or level (block) sensitive. Nevertheless, data blocks can
be transferred one data at time using an edge sensitive request signal.
A double buffering mechanism is available to deal with data blocks requiring the allocation of
2N addresses for the transfer of a N data block.
An interrupt can be used to warn AS-DSP that a predefined number of data have been
transferred and are ready to be processed. Interrupt requests are sent from the DMA controller
to the interrupt controller. The selected channels must be edge sensitive and the user has to
define the proper priority.
There are two ways to connect the DMA and the interrupt controllers, depending on the state
on the DIP_ENA static pin:
DIP_ENA = 0, there are enough available interrupt sources in the interrupt
controller: connect each DMA channel interrupt request (DITi, active on falling
Table 7.1
DMA Controller Interface Priority Levels
Priority
0
1
2
3
Channel
0
1
2
3
Level
Highest
Lowest
8
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