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參數(shù)資料
| 型號(hào)： | CYV15G0204RB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| 中文描述： | 獨(dú)立時(shí)鐘雙的HOTLink二⑩時(shí)鐘重計(jì)解串器 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 332K |
| 代理商： | CYV15G0204RB |
CYV15G0204RB
Document #: 38-02103 Rev. *C
Page 7 of 24
Pin Definitions
CYV15G0204RB Dual HOTLink II Deserializing Reclocker
Name
Receive Path Data and Status Signals
RXDA[9:0]
RXDB[9:0]
I/O Characteristics
Signal Description
LVTTL Output,
synchronous to the
RXCLK± output
Parallel Data Output
. RXDx[9:0] parallel data outputs change relative to the receive
interface clock. If RXCLKx± is a full-rate clock, the RXCLKx± clock outputs are
complementary clocks operating at the character rate. The RXDx[9:0] outputs for the
associated receive channels follow rising edge of RXCLKx+ or falling edge of
RXCLKx–. If RXCLKx± is a half-rate clock, the RXCLKx± clock outputs are comple-
mentary clocks operating at half the character rate. The RXDx[9:0] outputs for the
associated receive channels follow both the falling and rising edges of the associated
RXCLKx± clock outputs.
When BIST is enabled on the receive channel, the BIST status is presented on the
RXDx[1:0] and BISTSTx outputs. See
Table 5 on page 14
for each status reported
by the BIST state machine. Also, while BIST is enabled, the RXDx[9:2] outputs
should be ignored.
BIST Status Output.
When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0])
displays the status of the BIST reception. See
Table 5 on page 14
for the BIST status
reported for each combination of BISTSTx and RXDx[1:0].
When RXBISTx[1:0]
≠
10, BISTSTx should be ignored.
Reclocker Powered Down Status Output.
REPDOx is asserted HIGH, when the
associated channel’s reclocker output logic is powered down. This occurs when
ROE2x and ROE1x are both disabled by setting ROE2x = 0 and ROE1x = 0.
BISTSTA
BISTSTB
LVTTL Output,
synchronous to the
RXCLKx ± output
REPDOA
REPDOB
Asynchronous to
reclocker output
channel
enable / disable
Receive Path Clock Signals
TRGCLKA±
TRGCLKB±
Differential LVPECL
or single-ended
LVTTL input clock
CDR PLL Training Clock
. TRGCLKx± clock inputs are used as the reference source
for the frequency detector (Range Controller) of the associated receive PLL to
reduce PLL acquisition time.
In the presence of valid serial data, the recovered clock output of the receive CDR
PLL (RXCLKx±) has no frequency or phase relationship with TRGCLKx±.
When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock
source to either the true or complement TRGCLKx input, and leave the alternate
TRGCLKx input open (floating). When driven by an LVPECL clock source, the clock
must be a differential clock, using both inputs.
LVTTL Output Clock
Receive Clock Output
. RXCLKx± is the receive interface clock used to control
timing of the RXDx[9:0] parallel outputs. These true and complement clocks are used
to control timing of data output transfers. These clocks are output continuously at
either the half-character rate (1/20
th
the serial bit-rate) or character rate (1/10
th
the
serial bit-rate) of the data being received, as selected by RXRATEx.
LVTTL Output
Reclocker Clock Output
. RECLKOx output clock is synthesized by the associated
reclocker output PLL and operates synchronous to the internal recovered character
clock. RECLKOx operates at either the same frequency as RXCLKx± (RXRATEx =
0), or at twice the frequency of RXCLKx± (RXRATEx = 1).The reclocker clock outputs
have no fixed phase relationship to RXCLKx±.
Device Control Signals
RESET
LVTTL Input,
asynchronous,
internal pull-up
for a minimum pulse width. When the reset is removed, all state machines, counters
and configuration latches are at an initial state. As per the JTAG specifications the
device RESET cannot reset the JTAG controller. Therefore, the JTAG controller has
to be reset separately. Refer to
“JTAG Support” on page 14
for the methods to reset
the JTAG state machine.
See
Table 3 on page 13
for the initialize values of the device
configuration latches.
RXCLKA±
RXCLKB±
RECLKOA
RECLKOB
Asynchronous Device Reset
. RESET initializes all state machines, counters, and
configuration latches in the device to a known state. RESET must be asserted LOW
[+] Feedback
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| CYV15G0204RB-BGC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
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| CYV15G0204TRB | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CYV15G0204RB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II Reclocking Deserializer |
| CYV15G0204RB-BGC | 功能描述:視頻 IC 2x Indep Reclockers COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0204RB-BGXC | 功能描述:IC DESERIAL HOTLINK 256LBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| CYV15G0204TRB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| CYV15G0204TRB-BGC | 功能描述:視頻 IC 2x Indep Reclocker Serializer COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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