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參數(shù)資料
| 型號(hào)： | CYV15G0204RB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| 中文描述： | 獨(dú)立時(shí)鐘雙的HOTLink二⑩時(shí)鐘重計(jì)解串器 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 332K |
| 代理商： | CYV15G0204RB |
CYV15G0204RB
Document #: 38-02103 Rev. *C
Page 18 of 24
CYV15G0204RB AC Electrical Characteristics
Parameter
CYV15G0204RB Receiver LVTTL Switching Characteristics
Over the Operating Range
f
RS
RXCLKx± Clock Output Frequency
t
RXCLKP
RXCLKx± Period = 1/f
RS
t
RXCLKD
RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate)
t
RXCLKR [14]
RXCLKx± Rise Time
t
RXCLKF [14]
RXCLKx± Fall Time
t
RXDv–[18]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)
t
RXDv+[18]
Status and Data Valid Time to RXCLKx± (RXRATEx = 0) (Full Rate)
Status and Data Valid Time to RXCLKx± (RXRATEx = 1) (Half Rate)
f
ROS
RECLKOx Clock Frequency
t
RECLKO
RECLKOx Period=1/f
ROS
t
RECLKOD
RECLKOx Duty Cycle centered at 60% HIGH time
CYV15G0204RB TRGCLKx Switching Characteristics
Over the Operating Range
f
TRG
TRGCLKx Clock Frequency
t
TRGCLK
TRGCLKx Period = 1/f
REF
t
TRGH
TRGCLKx HIGH Time (TRGRATEx = 1)(Half Rate)
TRGCLKx HIGH Time (TRGRATEx = 0)(Full Rate)
t
TRGL
TRGCLKx LOW Time (TRGRATEx = 1)(Half Rate)
TRGCLKx LOW Time (TRGRATEx = 0)(Full Rate)
t
TRGD[20]
TRGCLKx Duty Cycle
t
TRGR [14, 15, 16, 17]
TRGCLKx Rise Time (20%–80%)
t
TRGF[14, 15, 16, 17]
TRGCLKx Fall Time (20%–80%)
t
TRGRX[21]
TRGCLKx Frequency Referenced to Received Clock Frequency
CYV15G0204RB Bus Configuration Write Timing Characteristics
Over the Operating Range
t
DATAH
Bus Configuration Data Hold
t
DATAS
Bus Configuration Data Setup
t
WRENP
Bus Configuration WREN Pulse Width
CYV15G0204RB JTAG Test Clock Characteristics
Over the Operating Range
f
TCLK
JTAG Test Clock Frequency
t
TCLK
JTAG Test Clock Period
CYV15G0204RB Device RESET Characteristics
Over the Operating Range
t
RST
Device RESET Pulse Width
Description
Min.
Max
Unit
9.75
6.66
–1.0
0.3
0.3
150
102.56
+1.0
1.2
1.2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
5UI–2.0
[19]
5UI–1.3
[19]
5UI–1.8
[19]
5UI–2.6
[19]
19.5
6.66
–1.9
150
51.28
0
19.5
6.6
5.9
2.9
[14]
5.9
2.9
[14]
30
150
51.28
MHz
ns
ns
ns
ns
ns
%
ns
ns
%
70
2
2
–0.15
+0.15
0
10
10
ns
ns
ns
20
MHz
ns
50
30
ns
Notes
14.Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
15.The ratio of rise time to falling time must not vary by greater than 2:1.
16.For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
17.All transmit AC timing parameters measured with 1ns typical rise time and fall time.
18.Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
19.Receiver UI (Unit Interval) is calculated as 1/(f
*20) (when TRGRATEx = 1) or 1/(f
TRG
* 10) (when TRGRATEx = 0). In an operating link this is equivalent to t
B
.
20.cycle cannot be as large as 30%–70%.
REFH
and t
REFL
21.TRGCLKx± has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
TRGCLKx± must be within
±
1500 PPM (
±
0.15%) of the transmitter PLL reference (REFCLKx±) frequency. Although transmitting to a HOTLink II receiver channel
necessitates the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be
within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV15G0204RB-BGC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB-BGXC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204TRB | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| CYV15G0204TRB-BGC | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| CYV15G0204TRB-BGXC | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0204RB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II Reclocking Deserializer |
| CYV15G0204RB-BGC | 功能描述:視頻 IC 2x Indep Reclockers COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0204RB-BGXC | 功能描述:IC DESERIAL HOTLINK 256LBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| CYV15G0204TRB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| CYV15G0204TRB-BGC | 功能描述:視頻 IC 2x Indep Reclocker Serializer COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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