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參數(shù)資料
| 型號(hào)： | CYV15G0204RB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| 中文描述： | 獨(dú)立時(shí)鐘雙的HOTLink二⑩時(shí)鐘重計(jì)解串器 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大小： | 332K |
| 代理商： | CYV15G0204RB |
CYV15G0204RB
Document #: 38-02103 Rev. *C
Page 9 of 24
DATA[6:0]
LVTTL input
asynchronous,
internal pull-up
Control Data Bus
. The DATA[6:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[6:0] bus into the latch
specified by address location on the ADDR[2:0] bus.
[3]
Table 3 on page 13
lists the
configuration latches within the device, and the initialization value of the latches upon
the assertion of RESET.
Table 4 on page 14
shows how the latches are mapped in
the device.
Internal Device Configuration Latches
RXRATE[A..B]
Internal Latch
[4]
SDASEL[2..1][A..B]
[1:0]
RXPLLPD[A..B]
Internal Latch
[4]
RXBIST[A..B][1:0]
Internal Latch
[4]
ROE2[A..B]
Internal Latch
[4]
ROE1[A..B]
Internal Latch
[4]
Factory Test Modes
SCANEN2
LVTTL input,
internal pull-down
TMEN3
LVTTL input,
internal pull-down
Analog I/O
ROUTA1±
ROUTB1±
Output
Receive Clock Rate Select
.
Signal Detect Amplitude Select
.
Internal Latch
[4]
Receive Channel Power Control
.
Receive Bist Disabled
.
Reclocker Differential Serial Output Driver 2 Enable
.
Reclocker Differential Serial Output Driver 1 Enable
.
Factory Test 2.
SCANEN2 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
Factory Test 3
. TMEN3 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
CML Differential
Primary Differential Serial Data Output
. The ROUTx1± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for
PECL-compatible connections.
Secondary Differential Serial Data Output
. The ROUTx2± PECL-compatible CML
outputs (+3.3V referenced) are capable of driving terminated transmission lines or
standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible
connections.
Primary Differential Serial Data Input
. The INx1± input accepts the serial data
stream for deserialization. The INx1± serial stream is passed to the receive CDR
circuit to extract the data content when INSELx = HIGH.
Secondary Differential Serial Data Input
. The INx2± input accepts the serial data
stream for deserialization. The INx2± serial stream is passed to the receiver CDR
circuit to extract the data content when INSELx = LOW.
ROUTA2±
ROUTB2±
CML Differential
Output
INA1±
INB1±
Differential Input
INA2±
INB2±
Differential Input
JTAG Interface
TMS
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-down
3-State LVTTL
Output
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-up
Test Mode Select
. Used to control access to the JTAG Test Modes. If maintained
high for
≥
5 TCLK cycles, the JTAG test controller is reset.
JTAG Test Clock
.
TCLK
TDO
Test Data Out
. JTAG data output buffer. High-Z while JTAG test mode is not
selected.
Test Data In
. JTAG data input port.
TDI
TRST
JTAG reset signal
. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
Note
4. See
“Device Configuration and Control Interface” on page 12
for detailed information on the internal latches.
Pin Definitions
(continued)
CYV15G0204RB Dual HOTLink II Deserializing Reclocker
Name
I/O Characteristics
Signal Description
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV15G0204RB-BGC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204RB-BGXC | Independent Clock Dual HOTLink II⑩ Reclocking Deserializer |
| CYV15G0204TRB | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| CYV15G0204TRB-BGC | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| CYV15G0204TRB-BGXC | Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0204RB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II Reclocking Deserializer |
| CYV15G0204RB-BGC | 功能描述:視頻 IC 2x Indep Reclockers COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0204RB-BGXC | 功能描述:IC DESERIAL HOTLINK 256LBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| CYV15G0204TRB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock HOTLink II⑩ Dual Serializer and Dual Reclocking Deserializer |
| CYV15G0204TRB-BGC | 功能描述:視頻 IC 2x Indep Reclocker Serializer COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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