參數(shù)資料
型號(hào): CYV15G0204RB
廠商: Cypress Semiconductor Corp.
英文描述: Independent Clock Dual HOTLink II⑩ Reclocking Deserializer
中文描述: 獨(dú)立時(shí)鐘雙的HOTLink二⑩時(shí)鐘重計(jì)解串器
文件頁數(shù): 17/24頁
文件大?。?/td> 332K
代理商: CYV15G0204RB
CYV15G0204RB
Document #: 38-02103 Rev. *C
Page 17 of 24
AC Test Loads and Waveforms
Differential CML Serial Outputs: ROUTA1
±
, ROUTA2
±
, ROUTB1
±
, ROUTB2
±
V
OHC
Output HIGH Voltage
(V
CC
Referenced)
100
Ω
differential load
150
Ω
differential load
100
Ω
differential load
150
Ω
differential load
100
Ω
differential load
150
Ω
differential load
V
CC
– 0.5
V
CC
– 0.5
V
CC
– 1.4
V
CC
– 1.4
450
560
V
CC
– 0.2
V
CC
– 0.2
V
CC
– 0.7
V
CC
– 0.7
900
1000
V
V
V
V
V
OLC
Output LOW Voltage
(V
CC
Referenced)
V
ODIF
Output Differential Voltage
|(OUT+)
(OUT
)|
mV
mV
Differential Serial Line Receiver Inputs: INA1
±
, INA2
±
, INB1
±
, INB2
±
V
DIFFs[7]
Input Differential Voltage |(IN+)
(IN
)|
V
IHE
Highest Input HIGH Voltage
V
ILE
Lowest Input LOW Voltage
I
IHE
Input HIGH Current
I
ILE
Input LOW Current
VI
COM[9]
Common Mode input range
100
1200
V
CC
mV
V
V
μ
A
μ
A
V
V
CC
– 2.0
V
IN
= V
IHE
Max.
V
IN
= V
ILE
Min.
((V
CC
– 2.0V)+0.5)min,
(V
CC
– 0.5V) max.
1350
–700
+1.25
+3.1
Power Supply
I
CC [10, 11]
Typ.
620
Max.
720
1320
700
1320
Max Power Supply Current
TRGCLKx =
MAX
Commercial
Industrial
Commercial
Industrial
mA
mA
mA
mA
I
CC [10, 11]
Typical Power Supply Current
TRGCLKx =
125 MHz
600
CYV15G0204RB DC Electrical Characteristics
(continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
Notes
9. The common mode range defines the allowable range of INPUT+ and INPUT
when INPUT+ = INPUT
. This marks the zero-crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
10.Maximum I
is measured with V
CC
= MAX, T
A
= 25°C, with both channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and
outputs unloaded.
11. Typical I
is measured under similar conditions except with V
= 3.3V, T
= 25°C, with both channels enabled and one Serial Line Driver per transmit channel
sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded.
12.Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
13.The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage.
2.0V
0.8V
GND
2.0V
0.8V
80%
20%
80%
20%
R
L
(Includes fixture and
probe capacitance)
3.0V
V
th
= 1.4V
270 ps
270 ps
[13]
V
th
= 1.4V
3.3V
R1
R2
R1 = 590
Ω
R2 = 435
Ω
C
L
7 pF
(Includes fixture and
probe capacitance)
(a) LVTTL Output Test Load
R
L
= 100
Ω
(b) CML Output Test Load
C
L
(c) LVTTL Input Test Waveform
(d) CML/LVPECL Input Test Waveform
1 ns
1 ns
V
IHE
V
ILE
V
IHE
V
ILE
[12]
[12]
[+] Feedback
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