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參數(shù)資料
| 型號： | CYV15G0104TRB-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock HOTLink II?? Serializer and Reclocking Deserializer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, BGA-256 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大小： | 985K |
| 代理商： | CYV15G0104TRB-BGC |
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PRELIMINARY
CYV15G0104TRB
Document #: 38-02100 Rev. **
Page 7 of 28
Pin Definitions
CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer
Name
Transmit Path Data and Status Signals
TXDB[9:0]
LVTTL Input,
synchronous,
sampled by
TXCLKB
↑
or
REFCLKB
↑
[2]
TXERRB
LVTTL Output,
synchronous to
REFCLKB
↑
[3]
,
asynchronous to
transmit channel
enable / disable,
asynchronous to loss
or return of
REFCLKB±
I/O Characteristics
Signal Description
Transmit Data Inputs
. TXDB[9:0] data inputs are captured on the rising edge of the
transmit interface clock. The transmit interface clock is selected by the TXCKSELB
latch via the device configuration interface.
Transmit Path Error
. TXERRB is asserted HIGH to indicate detection of a transmit
Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is
detected, TXERRB, is asserted HIGH and remains asserted until the transmit
Phase-Align Buffer is re-centered with the PABRSTB latch via the device configu-
ration interface. When TXBISTB = 0, the BIST progress is presented on the TXERRB
output. The TXERRB signal pulses HIGH for one transmit-character clock period to
indicate a pass through the BIST sequence once every 511 character times.
TXERRB is also asserted HIGH, when any of the following conditions is true:
The TXPLL is powered down. This occurs when TOE2B and TOE1B are both
disabled by setting TOE2B = 0 and TOE1B = 0.
The absence of the REFCLKB± signal.
Transmit Path Clock Signals
REFCLKB±
Differential LVPECL
or single-ended
LVTTL input clock
Reference Clock
. REFCLKB± clock inputs are used as the timing reference for the
transmit PLL. This input clock may also be selected to clock the transmit parallel
interface. When driven by a single-ended LVCMOS or LVTTL clock source, connect
the clock source to either the true or complement REFCLKB input, and leave the
alternate REFCLKB input open (floating). When driven by an LVPECL clock source,
the clock must be a differential clock, using both inputs.
Transmit Path Input Clock
. When configuration latch TXCKSELB = 0, the
associated TXCLKB input is selected as the character-rate input clock for the
TXDB[9:0] input. In this mode, the TXCLKB input must be frequency-coherent to its
TXCLKOB output clock, but may be offset in phase by any amount. Once initialized,
TXCLKB is allowed to drift in phase by as much as ±180 degrees. If the input phase
of TXCLKB drifts beyond the handling capacity of the Phase Align Buffer, TXERRB
is asserted to indicate the loss of data, and remains asserted until the Phase Align
Buffer is initialized. The phase of TXCLKB relative to REFCLKB± is initialized when
the configuration latch PABRSTB is written as 0. When TXERRB is deasserted, the
Phase Align Buffer is initialized and input characters are correctly captured.
Transmit Clock Output
. TXCLKOB output clock is synthesized by the transmit PLL
and operates synchronous to the internal transmit character clock. TXCLKOB
operates at either the same frequency as REFCLKB± (TXRATEB = 0), or at twice
the frequency of REFCLKB± (TXRATEB = 1). The transmit clock outputs have no
fixed phase relationship to REFCLKB±.
TXCLKB
LVTTL Clock Input,
internal pull-down
TXCLKOB
LVTTL Output
Receive Path Data and Status Signals
RXDA[9:0]
LVTTL Output,
synchronous to the
RXCLKA ± output
Parallel Data Output
. RXDA[9:0] parallel data outputs change relative to the receive
interface clock. If RXCLKA± is a full-rate clock, the RXCLKA± clock outputs are
complementary clocks operating at the character rate. The RXDA[9:0] outputs for
the associated receive channels follow rising edge of RXCLKA+ or falling edge of
RXCLKA–. If RXCLKA± is a half-rate clock, the RXCLKA± clock outputs are comple-
mentary clocks operating at half the character rate. The RXDA[9:0] outputs for the
associated receive channels follow both the falling and rising edges of the
associated RXCLKA± clock outputs.
When BIST is enabled on the receive channel, the BIST status is presented on the
RXDA[1:0] and BISTSTA outputs. See
Table 6
for each status reported by the BIST
state machine. Also, while BIST is enabled, the RXDA[9:2] outputs should be
ignored.
Notes:
2.
3.
When REFCLKB± is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKB±.
When REFCLKB± is configured for half-rate operation, this output is presented relative to both the rising and falling edges of the associated REFCLKB±.
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| CYV15G0404RB-BGXC | Independent Clock Quad HOTLink II⑩ Deserializing Reclocker |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYV15G0104TRB-BGXC | 功能描述:視頻 IC 1x Indep Reclocker Serializer COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CYV15G0201DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Dual-channel HOTLink II⑩ Transceiver |
| CYV15G0201DXB-BBC | 功能描述:電信線路管理 IC Dual Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0201DXB-BBI | 制造商:Cypress Semiconductor 功能描述: |
| CYV15G0201DXB-BBXC | 功能描述:電信線路管理 IC Dual Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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