參數(shù)資料
型號(hào)： CYV15G0104TRB-BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Independent Clock HOTLink II?? Serializer and Reclocking Deserializer
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.57 MM HEIGHT, BGA-256
文件頁(yè)數(shù)： 12/28頁(yè)
文件大?。?/td> 985K
代理商： CYV15G0104TRB-BGC
PRELIMINARY
CYV15G0104TRB
Document #: 38-02100 Rev. **
Page 12 of 28
CYV15G0104TRB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INA1± and INA2±, are
available on the receive channel for accepting serial data
streams. The active Serial Line Receiver is selected using the
INSELA input. The Serial Line Receiver inputs are differential,
and can accommodate wire interconnect and filtering losses
or transmission line attenuation greater than 16 dB. For
normal operation, these inputs should receive a signal of at
least VI
DIFF
> 100 mV, or 200 mV peak-to-peak differential.
Each Line Receiver can be DC- or AC-coupled to +3.3V
powered fiber-optic interface modules (any ECL/PECL family,
not limited to 100K PECL) or AC-coupled to +5V powered
optical modules. The common-mode tolerance of these line
receivers accommodates a wide range of signal termination
voltages. Each receiver provides internal DC-restoration, to
the center of the receiver’s common mode range, for AC-
coupled signals.
Signal Detect/Link Fault
Each selected Line Receiver (i.e., that routed to the clock and
data recovery PLL) is simultaneously monitored for
analog amplitude above amplitude level selected by
SDASELA
transition density above the specified limit
range controls report the received data stream inside
normal frequency range (±1500 ppm
[24]
)
receive channel enabled
Presence of reference clock
ULCA is not asserted.
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIA (Link Fault Indicator) output associated with each
receive channel, which changes synchronous to the receive
interface clock.
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow
operation with highly attenuated signals, or in high-noise
environments. The analog amplitude level detection is set by
the SDASELA latch via device configuration interface. The
SDASELA latch sets the trip point for the detection of a valid
signal at one of three levels, as listed in
Table 2
. This control
input affects the analog monitors for all receive channels. The
Analog Signal Detect monitors are active for the Line Receiver
as selected by the INSELA input.
Transition Density
The Transition Detection logic checks for the absence of
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received, the
Detection logic for that channel asserts LFIA.
Range Controls
The CDR circuit includes logic to monitor the frequency of the
PLL Voltage Controlled Oscillator (VCO) used to sample the
incoming data stream. This logic ensures that the VCO
operates at, or near the rate of the incoming data stream for
two primary cases:
when the incoming data stream resumes after a time in
which it has been “missing.”
when the incoming data stream is outside the acceptable
signaling rate range.
To perform this function, the frequency of the RXPLL VCO is
periodically compared to the frequency of the TRGCLKA±
input. If the VCO is running at a frequency beyond
±1500ppm
[24]
as defined by the TRGCLKA± frequency, it is
periodically forced to the correct frequency (as defined by
TRGCLKA±, SPDSELA, and TRGRATEA) and then released
in an attempt to lock to the input data stream.
The sampling and relock period of the Range Control is calcu-
lated as follows: RANGE_CONTROL_ SAMPLING_PERIOD
= (RECOVERED BYTE CLOCK PERIOD) * (4096).
During the time that the Range Control forces the RXPLL VCO
to track TRGCLKA±, the LFIA output is asserted LOW. After a
valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIA should be
HIGH.
The operating serial signaling-rate and allowable range of
TRGCLKA± frequencies are listed in
Table 3
.
Receive Channel Enabled
The receive channel can be enabled or disabled through the
RXPLLPDA input latch as controlled by the device configu-
ration interface. When RXPLLPDA = 0, the CDR PLL and
analog circuitry of the channel are disabled. Any disabled
channel indicates a constant link fault condition on the LFIA
output. When RXPLLPDA = 1, the CDR PLL and receive
channel are enabled to receive a serial stream.
Note:
7.
The peak amplitudes listed in this table are for typical waveforms that have generally 3 – 4 transitions for every ten bits. In a worse case environment the signals
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
Table 2. Analog Amplitude Detect Valid Signal Levels
[7]
SDASE-
LA
00
01
10
11
Typical Signal with Peak Amplitudes
Above
Analog Signal Detector is disabled
140 mV p-p differential
280 mV p-p differential
420 mV p-p differential
Table 3. Operating Speed Settings
SPDSELA
LOW
TRGRATEA
1
0
1
0
1
0
TRGCLKA±
Frequency
(MHz)
reserved
19.5 – 40
20 – 40
40 – 80
40 – 75
80 – 150
Signaling
Rate (Mbps)
195 – 400
MID (Open)
400 – 800
HIGH
800 – 1500
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CYV15G0104TRB-BGXC 功能描述:視頻 IC 1x Indep Reclocker Serializer COM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
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CYV15G0201DXB-BBC 功能描述:電信線路管理 IC Dual Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYV15G0201DXB-BBI 制造商:Cypress Semiconductor 功能描述:
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