
PRELIMINARY
CYV15G0104TRB
Document #: 38-02100 Rev. **
Page 10 of 28
CYV15G0104TRB HOTLink II Operation
The CYV15G0104TRB is a highly configurable, independent
clocking device designed to support reliable transfer of large
quantities of digital video data, using high-speed serial links
from multiple sources to multiple destinations.
ROE2A
ROE1A
PABRSTB
Factory Test Modes
SCANEN2
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Reclocker Differential Serial Output Driver 2 Enable
.
Reclocker Differential Serial Output Driver 1 Enable
.
Transmit Clock Phase Alignment Buffer Reset
.
LVTTL input,
internal pull-down
LVTTL input,
internal pull-down
Factory Test 2.
SCANEN2 input is for factory testing only. This input may be left as
a NO CONNECT, or GND only.
Factory Test 3
. TMEN3 input is for factory testing only. This input may be left as a
NO CONNECT, or GND only.
TMEN3
Analog I/O
TOUTB1±
CML Differential
Output
Transmitter Primary Differential Serial Data Output
. The transmitter TOUTB1±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be AC-
coupled for PECL-compatible connections.
Transmitter Secondary Differential Serial Data Output
. The transmitter TOUTB2±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be AC-coupled
for PECL-compatible connections.
Reclocker Primary Differential Serial Data Output
. The reclocker ROUTA1±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be AC-
coupled for PECL-compatible connections.
Reclocker Secondary Differential Serial Data Output
. The reclocker ROUTA2±
PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated
transmission lines or standard fiber-optic transmitter modules, and must be AC-coupled
for PECL-compatible connections.
Primary Differential Serial Data Input
. The INA1± input accepts the serial data
stream for deserialization. The INA1± serial stream is passed to the receive CDR
circuit to extract the data content when INSELA = HIGH.
Secondary Differential Serial Data Input
. The INA2± input accepts the serial data
stream for deserialization. The INA2± serial stream is passed to the receiver CDR
circuit to extract the data content when INSELA = LOW.
TOUTB2±
CML Differential
Output
ROUTA1±
CML Differential
Output
ROUTA2±
CML Differential
Output
INA1±
Differential Input
INA2±
Differential Input
JTAG Interface
TMS
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-down
3-State LVTTL
Output
LVTTL Input,
internal pull-up
LVTTL Input,
internal pull-up
Test Mode Select
. Used to control access to the JTAG Test Modes. If maintained
high for
≥
5 TCLK cycles, the JTAG test controller is reset.
JTAG Test Clock
.
TCLK
TDO
Test Data Out
. JTAG data output buffer. High-Z while JTAG test mode is not
selected.
Test Data In
. JTAG data input port.
TDI
TRST
JTAG reset signal
. When asserted (LOW), this input asynchronously resets the
JTAG test access port controller.
Power
V
CC
GND
+3.3V Power
.
Signal and Power Ground for all internal circuits
.
Pin Definitions
(continued)
CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer
Name
I/O Characteristics
Signal Description