參數(shù)資料
型號(hào)： CYP15G0101DXA
廠商： Cypress Semiconductor Corp.
英文描述： Single Channel HOTLink II Transceiver
中文描述： 單通道HOTLink II收發(fā)器
文件頁(yè)數(shù)： 29/40頁(yè)
文件大?。?/td> 527K
代理商： CYP15G0101DXA
CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 29 of 40
CYP15G0101DXA HOTLink II Transmitter Switching Waveforms
(continued)
TXCLKO
t
TXCLKO
t
TXCLKOD+
t
TXCLKOD
–
Transmit Interface
TXCLKO Timing
TXCKSEL = LOW
TXRATE = LOW
REFCLK
Note 33
Note 34
t
REFCLK
t
REFH
t
REFL
Switching Waveforms for the CYP15G0101DXA HOTLink II Receiver
Note:
35. RXCLK and RXCLKC are a delayed in phase from REFCLK, and are different in phase from each other.
36. When operated with a half-rate REFCLK, the setup and hold specifications for data relative to RXCLK and RXCLKC are relative to both rising and falling
edges of the clock output
REFCLK
RXD[7:0],
RXST[2:0],
RXOP
t
RREFDV
t
REFCLK
t
REFH
t
REFL
Receive Interface
Read Timing
RXCKSEL = LOW
RXRATE = LOW
RXCLK
RXCLKC
t
REFADV+
t
REFCDV+
t
REFADV
–
t
REFCDV
–
Note 35
t
RREFDA
REFCLK
RXD[7:0],
RXST[2:0],
RXOP
t
RREFDV
t
REFCLK
t
REFH
t
REFL
Receive Interface
Read Timing
RXCKSEL = LOW
TXRATE = HIGH
t
RREFDA
t
RREFDV
RXCLK
RXCLKC
t
REFADV+
t
REFCDV+
t
REFADV
–
t
REFCDV
–
Note 35
Note 36
t
RREFDA
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PDF描述
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參數(shù)描述
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