參數(shù)資料
型號: CYP15G0101DXA
廠商: Cypress Semiconductor Corp.
英文描述: Single Channel HOTLink II Transceiver
中文描述: 單通道HOTLink II收發(fā)器
文件頁數(shù): 27/40頁
文件大?。?/td> 527K
代理商: CYP15G0101DXA
CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 27 of 40
CYP15G0101DXA Receive Serial Inputs and CDR PLL Characteristics
Over the Operating Range
Parameter
Description
Min.
Max.
Unit
t
RXLOCK
Receive PLL lock to input data stream (cold start)
10
ms
Receive PLL lock to input data stream
2500
UI
t
RXUNLOCK
t
SA
t
jtol
Receive PLL Unlock Rate
Static Alignment
[17, 28]
Jitter Tolerance
[17, 29, 30, 31]
TBD
TBD
ns
TBD
TBD
ps
TBD
TBD
UI
Notes:
28. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in
3,000 nominal transitions until a character error occurs.
29. Receiver UI (Unit Interval) is calculated as 1/(f
*20) (when RXRATE
=
HIGH) or 1/(f
* 10) (when RXRATE
=
LOW) if no data is being received, or 1/(f
* 20)
(when RXRATE
HIGH) or 1/(f
* 10) (when RXRATE
LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to t
B
.
30. All measurements were done using a CJTPAT.
31. Measured at a datarate of 1.25Gbps.
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