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參數(shù)資料
| 型號： | CYP15G0101DXA |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Single Channel HOTLink II Transceiver |
| 中文描述： | 單通道HOTLink II收發(fā)器 |
| 文件頁數(shù)： | 18/40頁 |
| 文件大?。?/td> | 527K |
| 代理商： | CYP15G0101DXA |
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CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 18 of 40
The specific status reported by the BIST state machine are
listed in
Table 17
. These same codes are reported on the re-
ceive status outputs regardless of the state of DECMODE.
The specific patterns checked by each receiver are described
in detail in the Cypress application note
“
HOTLink Built-In Self-
Test.
”
The sequence compared by the CYP15G0101DXA is
identical to that in the CY7B933 and CY7C924DX, allowing
interoperable systems to be built when used at compatible se-
rial signaling rates.
If the number of invalid characters received ever exceeds the
number of valid characters by 16, the receive BIST state ma-
chine aborts the compare operations and resets the LFSR to
the D0.0 state to look for the start of the BIST sequence again.
When the receive paths are configured for common clock op-
eration (RXCKSEL = LOW) each pass must be preceded by a
16-character Word Sync Sequence to allow output buffer
alignment and management of clock frequency variations.
This is automatically generated by the transmitter when its lo-
cal RXCKSEL = LOW.
The BIST state machine requires the characters to be correctly
framed for it to detect the BIST sequence. If the Low-Latency
Framer is enabled (RFMODE = LOW), the Framer will mis-
align to an aliased SYNC character within the BIST sequence.
If the Alternate-mode Multi-Byte Framer is enabled
(RFMODE = HIGH) and the Receiver outputs are clocked rel-
ative to a recovered clock (RXCKSEL
=
MID), it is generally
necessary to frame the Receiver before BIST is enabled. If the
Receiver outputs are clocked relative to REFCLK
(RXCKSEL = LOW), the transmitter precedes every 511 char-
acter BIST sequence with a 16-character Word Sync Se-
quence. This sequence will frame the Receiver regardless of
the setting of RFMODE.
Receive Elasticity Buffer
The receive channel contains an Elasticity Buffer that is de-
signed to support multiple clocking modes. This buffer allows
data to be read using an Elasticity Buffer read-clock that is
asynchronous in both frequency and phase from the Elasticity
Buffer write clock, or to use a read clock that is frequency
coherent but with uncontrolled phase relative to the Elasticity
Buffer write clock.
The Elasticity Buffer is a minimum of 10-characters deep, and
supports a 12-bit wide data path. It is capable of supporting a
decoded character, three status bits, and a parity bit for each
character present in the buffer. The write clock for this buffer
is always the recovered clock for the read channel.
The read clock for the Elasticity Buffer may come from one of
two selectable sources. It may be a
character-rate REFCLK
recovered clock from the receive channel
Receive Modes
The operating mode of the receive path is set through the
RXMODE input. This RXMODE input is only interpreted when
the Decoder is enabled (DECMODE
≠
LOW). These modes
determine the RXST status reporting. The different receive
modes are listed in
Table 13
.
When RXCKSEL = LOW, the Receive channel is clocked by
REFCLK. The RXCLK
±
and RXCLKC+ outputs presents buff-
ered and delayed forms of REFCLK. In this mode, the receive
Elasticity Buffer is enabled. For REFCLK clocking, the Elastic-
ity Buffer must be able to insert K28.5 characters and delete
framing characters as appropriate.
The insertion of a K28.5 or deletion of a framing character can
occur at any time, however, the actual timing on these inser-
tions and deletions is controlled in part by the how the trans-
mitter sends its data. Insertion of a K28.5 character can only
occur when the receiver has a framing character in the Elas-
ticity Buffer. Likewise, to delete a framing character, one must
also be in the Elasticity Buffer. To prevent an Elasticity Buffer
overflow or underflow in the receive channel, a minimum den-
sity of framing characters must be present in the received data
stream.
Prior to reception of valid data, at least one Word Sync Se-
quence (or that portion of one necessary to center the Elastic-
ity Buffer) must be received to allow the receive Elasticity Buff-
er to be centered. The Elasticity Buffer may also be centered
by a device reset operation initiated through the TRSTZ input,
however, following such an event the CYP15G0101DXA will
normally require a framing event before it will correctly decode
characters.
When RXCKSEL = MID (or open), the received channel Out-
put Register is clocked by the recovered clock. Since no char-
acters may be added or deleted, the receiver Elasticity Buffer
is bypassed.
Power Control
The CYP15G0101DXA supports user control of the powered
up or down state of the Transmit and Receive channel. The
Receive channel is controlled by the RXLE signal and the val-
ues present on the BOE[1:0] bus. The Transmit channel is
controlled by the OELE signal and the values present on the
BOE[1:0] bus. If either the Transmit or the Receive channel is
not used, then powering down the unused channel will save
power and reduce system heat generation. Controlling system
power dissipation will improve the system performance.
Receive Channel
When RXLE = HIGH, the signal on the BOE[0] input directly
controls the power enable for the receive PLL and the analog
circuit. When BOE[0] = HIGH, the Receive channel and its an-
alog circuits are active. When BOE[0] = LOW, the Receive
channel and its analog circuits are powered down. When a
disabled receive channel is re-enabled, the status of the LFI
output and data on the parallel outputs for the Receive channel
may be indeterminate for up to 10 ms.
Transmit Channel
When OELE = HIGH, the signals on the BOE[1:0] inputs
directly control the power enables for the Serial Drivers. When
a BOE[1:0] input is HIGH, the associated Serial Driver is en-
Table 13. Receive Operating Modes
RX Mode
Operating Mode
M
N
R
Channel Mode
Independent
RXST Status Reporting
Status A
Reserved for test
Status B
0
1
2
L
M
H
Independent
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