參數(shù)資料
型號(hào)： CYP15G0101DXA
廠商： Cypress Semiconductor Corp.
英文描述： Single Channel HOTLink II Transceiver
中文描述： 單通道HOTLink II收發(fā)器
文件頁(yè)數(shù)： 24/40頁(yè)
文件大?。?/td> 527K
代理商： CYP15G0101DXA
CYP15G0101DXA
PRELIMINARY
Document #: 38-02061 Rev. **
Page 24 of 40
V
ODIF
Output Differential Voltage
|(OUT+)
(OUT
)|
100
differential load
150
differential load
450
560
800
1000
mV
mV
Differential Serial Line Receiver Inputs: IN1
±
, IN2
±
V
DIFFS [12]
Input Differential Voltage |(IN+)
(IN
)|
V
IHE
Highest Input HIGH Voltage
V
ILE
Lowest Input LOW Voltage
I
IHE
Input HIGH Current
I
ILE
Input LOW Current
V
COM [14]
Common mode Input range
100
1200
V
CC
mV
V
V
μ
A
μ
A
V
V
CC
2.0
V
IN
=V
IHE
Max.
V
IN
=V
ILE
Min.
((V
CC
2.0) + 0.05) Min.,
(Min. V
CC
0.05) Max.
1350
700
+1.25
+3.1
Miscellaneous
I
CC [15]
Typ.
Max.
305
TBD
Power Supply Current
REFCLK=
Max.
Commercial
Industrial
mA
mA
mA
I
CC [16]
Typ Power Supply Current
REFCLK=
125 MHz
260
CYP15G0101DXA DC Electrical Characteristics
Over the Operating Range
(continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
Capacitance
[17]
Parameter
C
INTTL
C
INPECL
Description
Test Conditions
Max.
7
4
Unit
pF
pF
TTL Input Capacitance
PECL input Capacitance
T
A
= 25
°
C, f
0
= 1 MHz, V
CC
= 3.3V
T
A
= 25
°
C, f
0
= 1 MHz, V
CC
= 3.3V
AC Test Loads and Waveforms
Notes:
14. The common mode range defines the allowable range of INPUT+ and INPUT
when INPUT+ = INPUT
. This marks the zero-crossing between the true and
complement inputs as the signal switches between a logic-1 and a logic-0.
15. Maximum I
is measured with V
CC
=
MAX, RFEN
=
LOW, TA
=
25
°
C, with all Serial Line Drivers enabled, sending a constant alternating 01 pattern, and
outputs unloaded.
16. Typical I
is measured under similar conditions except with V
CC
=
3.3V, TA
=
25
°
C, RFEN
=
LOW, with one Serial Line Driver sending a continuous
alternating 01 pattern and parallel outputs unloaded.
17. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
18. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
19. The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the signal edges crosses this threshold voltage.
2.0V
0.8V
GND
2.0V
0.8V
80%
20%
80%
20%
R
L
(Includes fixture and
probe capacitance)
3.0V
V
th
= 1.4V
≤
270 ps
≤
270 ps
Note 19
V
th
= 1.4V
3.3V
R1
R2
R1 = 590
R2 = 435
C
L
≤
7 pF
(Includes fixture and
probe capacitance)
(a) LVTTL Output Test Load
R
L
= 100
C
L
<
5 pF
(b) CML Output Test Load
C
L
C
L
(c) LVTTL Input Test Waveform
(d) CML/LVPECL Input Test Waveform
≤
1 ns
≤
1 ns
V
IHE
V
ILE
V
IHE
V
ILE
Note 18
Note 18
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