參數(shù)資料
型號(hào)： CYD04S36V
廠商： Cypress Semiconductor Corp.
英文描述： FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36同步雙端口RAM)
中文描述： FLEx36TM 3.3 32K/64K/128K/256K/512 × 36同步雙口RAM（FLEx36TM 3.3 32K/64K/128K/256K/512 × 36同步雙端口RAM）的
文件頁數(shù)： 6/28頁
文件大?。?/td> 608K
代理商： CYD04S36V
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Document #: 38-06076 Rev. *E
Page 6 of 28
Counter enable (CNTEN) inputs are provided to stall the
operation of the address input and utilize the internal address
generated by the internal counter for fast, interleaved memory
applications. A port’s burst counter is loaded when the port’s
address strobe (ADS) and CNTEN signals are LOW. When the
port’s CNTEN is asserted and the ADS is deasserted, the
address counter will increment on each LOW to HIGH
transition of that port’s clock signal. This will Read/Write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array, and will loop back to the start. Counter reset (CNTRST)
is used to reset the unmasked portion of the burst counter to
0s. A counter-mask register is used to control the counter
wrap.
Counter Reset Operation
All unmasked bits of the counter and mirror registers are reset
to “0.” All masked bits remain unchanged. A Mask Reset
followed by a Counter Reset will reset the counter and mirror
registers to 00000, as will master reset (MRST).
Counter Load Operation
The address counter and mirror registers are both loaded with
the address value presented at the address lines.
Table 3. Address Counter and Counter-Mask Register Control Operation (Any Port)
[18, 20]
CLK
X
MRST
L
CNT/MSK
X
CNTRST
X
ADS
X
CNTEN
X
Operation
Master Reset
Description
Reset address counter to all 0s and mask
register to all 1s.
Reset counter unmasked portion to all 0s.
H
H
L
X
X
Counter Reset
H
H
H
L
L
Counter Load
Load counter with external address value
presented on address lines.
Counter Readback Read out counter internal value on address
lines.
Counter Increment Internally increment address counter value.
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
Counter Hold
Constantly hold the address value for
multiple clock cycles.
Reset mask register to all 1s.
H
L
L
X
X
Mask Reset
H
L
H
L
L
Mask Load
Load mask register with value presented on
the address lines.
Read out mask register value on address
lines.
Operation undefined
H
L
H
L
H
Mask Readback
H
L
H
H
X
Reserved
Notes:
20.Counter operation and mask register operation is independent of chip enables.
相關(guān)PDF資料
PDF描述
CYD09S36V FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36同步雙端口RAM)
CYD18S72V18 FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
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CYD09S72V18 FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYD04S36V-133BBC 制造商:Cypress Semiconductor 功能描述:
CYD04S36V-133BBI 制造商:Cypress Semiconductor 功能描述:
CYD04S36V-167BBC 制造商:Cypress Semiconductor 功能描述:
CYD04S36V18 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mb/9-Mb/4-Mb x36/x18 FullFlex⑩ Dual-Ports
CYD04S36V18-167BBXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4M Sync Dual Port 128Kx36 90nm COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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