參數(shù)資料
型號: CYD04S36V
廠商: Cypress Semiconductor Corp.
英文描述: FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36同步雙端口RAM)
中文描述: FLEx36TM 3.3 32K/64K/128K/256K/512 × 36同步雙口RAM(FLEx36TM 3.3 32K/64K/128K/256K/512 × 36同步雙端口RAM)的
文件頁數(shù): 21/28頁
文件大小: 608K
代理商: CYD04S36V
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Document #: 38-06076 Rev. *E
Page 21 of 28
Readback State of Address Counter or Mask Register
[46, 47, 48, 49]
Notes:
46.CE
= OE = BE0 – BE3 = LOW; CE
= R/W = CNTRST = MRST = HIGH.
47.Address in output mode. Host must not be driving address bus after t
CKLZ
in next clock cycle.
48.Address in input mode. Host can drive address bus after t
.
49.An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.
Switching Waveforms
(continued)
CNTEN
CLK
t
CH2
t
CL2
t
CYC2
ADDRESS
A
0
–A
16
ADS
A
n
Q
x-2
Q
x-1
Q
n
t
SA
t
HA
t
SAD
t
HAD
t
SCN
t
HCN
LOAD
EXTERNAL
ADDRESS
t
CD2
INTERNAL
ADDRESS
A
n+1
A
n+2
A
n
t
CKHZ
DATA
OUT
A
n*
Q
n+3
Q
n+1
Q
n+2
A
n+3
A
n+4
t
CKLZ
t
CA2
or t
CM2
READBACK
COUNTER
INTERNAL
ADDRESS
INCREMENT
EXTERNAL
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