參數(shù)資料
型號(hào)： CYD36S72V18
廠商： Cypress Semiconductor Corp.
英文描述： FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
中文描述： FullFlex器件特別提款權(quán)同步雙端口SRAM（FullFlex器件同步雙端口SRAM的特別提款權(quán)）
文件頁(yè)數(shù)： 1/52頁(yè)
文件大?。?/td> 774K
代理商： CYD36S72V18
FullFlex Synchronous
SDR Dual-Port SRAM
FullFlex
Cypress Semiconductor Corporation
Document #: 38-06082 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 6, 2006
Features
True dual-ported memory allows simultaneous access
to the shared array from each port
Synchronous pipelined operation with Single Data Rate
(SDR) operation on each port
— SDR interface at 250 MHz
— Up to 36-Gb/s bandwidth (250 MHz * 72 bit * 2 ports)
Selectable pipelined or flow-through mode
1.5V or 1.8V core power supply
Commercial and Industrial temperature
IEEE 1149.1 JTAG boundary scan
Available in 484-ball PBGA Packages and 256-ball
FBGA packages
FullFlex72 family
— 36-Mbit: 512K x 72 (CYD36S72V18)
— 18-Mbit: 256K x 72 (CYD18S72V18)
— 9-Mbit: 128K x 72 (CYD09S72V18)
— 4-Mbit: 64K x 72 (CYD04S72V18)
FullFlex36 family
— 36-Mbit: 1M x 36 (CYD36S36V18)
— 18-Mbit: 512K x 36 (CYD18S36V18)
— 9-Mbit: 256K x 36 (CYD09S36V18)
— 4-Mbit: 128K x 36 (CYD04S36V18)
FullFlex18 family
— 36-Mbit: 2M x 18 (CYD36S18V18)
— 18-Mbit: 1M x 18 (CYD18S18V18)
— 9-Mbit: 512K x 18 (CYD09S18V18)
— 4-Mbit: 256K x 18 (CYD04S18V18)
Built-in deterministic access control to manage
address collisions
— Deterministic flag output upon collision detection
— Collision detection on back-to-back clock cycles
— First Busy Address readback
Advanced features for improved high-speed data
transfer and flexibility
— Variable Impedance Matching (VIM)
— Echo clocks
— Selectable LVTTL (3.3V), Extended HSTL
(1.4V–1.9V), 1.8V LVCMOS, or 2.5V LVCMOS I/O on
each port
— Burst counters for sequential memory access
— Mailbox with interrupt flags for message passing
— Dual Chip Enables for easy depth expansion
Functional Description
The FullFlex Dual-Port SRAM families consist of 4-Mbit,
9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual-port static
RAMs that are high-speed, low-power 1.8V/1.5V CMOS. Two
ports are provided, allowing the array to be accessed simulta-
neously. Simultaneous access to a location triggers determin-
istic access control. For FullFlex72 these ports can operate
independently with 72-bit bus widths and each port can be
independently configured for two pipelined stages. Each port
can also be configured to operate in pipelined or flow-through
mode.
Advanced features include built-in deterministic access
control to manage address collisions during simultaneous
access to the same memory location, Variable Impedance
Matching (VIM) to improve data transmission by matching the
output driver impedance to the line impedance, and echo
clocks to improve data transfer.
To reduce the static power consumption, chip enables can be
used to power down the internal circuitry. The number of
cycles of latency before a change in CE0 or CE1 will enable
or disable the databus matches the number of cycles of read
latency selected for the device. In order for a valid write or read
to occur, both chip enable inputs on a port must be active.
Each port contains an optional burst counter on the input
address register. After externally loading the counter with the
initial address, the counter will increment the address inter-
nally.
Additional features of this device include a mask register and
a mirror register to control counter increments and
wrap-around. The counter-interrupt (CNTINT) flags notify the
host that the counter will reach maximum count value on the
next clock cycle. The host can read the burst-counter internal
address, mask register address, and busy address on the
address lines. The host can also load the counter with the
address stored in the mirror register by utilizing the retransmit
functionality. Mailbox interrupt flags can be used for message
passing, and JTAG boundary scan and asynchronous Master
Reset (MRST) are also available. The logic block diagram in
Figure 1
displays these features.
The FullFlex72 is offered in a 484-ball plastic BGA package.
The FullFlex36 and FullFlex18 are offered in both 484-ball and
256-ball fine pitch BGA packages.
相關(guān)PDF資料
PDF描述
CYD09S72V18 FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
CYD36S18V18 FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
CYD36S36V18 FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM)
CYD18S72V FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM(FLEx72 3.3V 64K/128K/256K x 72同步雙端口RAM)
CYD09S72V FLEx72 3.3V 64K/128K/256K x 72 Synchronous Dual-Port RAM(FLEx72 3.3V 64K/128K/256K x 72同步雙端口RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYD36S72V18-167BGXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512K x 72 90nm SDR 36M SYNC DUAL PORT RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CYD36S72V18-167BGXI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB (512Kx72) 1.8v 167MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CYD36S72V18-200BGXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB (512Kx72) 1.8v 200MHz Sync 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CYDC064B08 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
CYDC064B08-40AXC 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM
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