參數(shù)資料
型號(hào)： CYD04S36V
廠商： Cypress Semiconductor Corp.
英文描述： FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36同步雙端口RAM)
中文描述： FLEx36TM 3.3 32K/64K/128K/256K/512 × 36同步雙口RAM（FLEx36TM 3.3 32K/64K/128K/256K/512 × 36同步雙端口RAM）的
文件頁(yè)數(shù)： 4/28頁(yè)
文件大?。?/td> 608K
代理商： CYD04S36V
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Document #: 38-06076 Rev. *E
Page 4 of 28
Pin Definitions
Left Port
A
0L
–A
18L
BE
0L
–BE
3L
Right Port
A
0R
–A
18R
BE
0R
–BE
3R
Description
Address Inputs
.
Byte Enable Inputs
. Asserting these signals enables Read and Write operations
to the corresponding bytes of the memory array.
BUSY
L[2,5]
C
L
CE0
L[11]
CE1
L[10]
DQ
0L
–DQ
35L
OE
L
BUSY
R[2,5]
C
R
CE0
R[11]
CE1
R[10]
DQ
0R
–DQ
35R
OE
R
Port Busy Output
.
When the collision is detected, a BUSY is asserted.
Input Clock Signal
.
Active Low Chip Enable Input
.
Active High Chip Enable Input
.
Data Bus Input/Output
.
Output Enable Input
. This asynchronous signal must be asserted LOW to enable
the DQ data pins during Read operations.
Mailbox Interrupt Flag Output
.
The mailbox permits communications between
ports. The upper two memory locations can be used for message passing. INT
L
is
asserted LOW when the right port writes to the mailbox location of the left port, and
vice versa. An interrupt to a port is deasserted HIGH when it reads the contents of
its mailbox.
Port Low Speed Select Input
.
PORTSTD[1:0]
R[2,4]
Port Address/Control/Data I/O Standard Select Inputs
.
R/W
R
Read/Write Enable Input
. Assert this pin LOW to write to, or HIGH to Read from
the dual port memory array.
READY
R[2,5]
Port Ready Output
.
This signal will be asserted when a port is ready for normal
operation.
CNT/MSK
R[10]
Port Counter/Mask Select Input
.
Counter control input.
ADS
R[11]
Port Counter Address Load Strobe Input
.
Counter control input.
CNTEN
R[11]
Port Counter Enable Input
.
Counter control input.
CNTRST
R[10]
Port Counter Reset Input
. Counter control input.
CNTINT
R[12]
Port Counter Interrupt Output
. This pin is asserted LOW when the unmasked
portion of the counter is incremented to all “1s”.
WRP
R[2,3]
Port Counter Wrap Input
.
The burst counter wrap control input.
RET
R[2,3]
Port Counter Retransmit Input
.
Counter control input.
FTSEL
R[2,3]
Flow-Through Select
. Use this pin to select Flow-Through mode. When is
de-asserted, the device is in pipelined mode.
VREF
R[2,4]
Port External High-Speed IO Reference Input
.
V
DDIOR
Port IO Power Supply
.
REV
R[2, 3, 4]
Reserved pins for future features.
MRST
Master Reset Input
. MRST is an asynchronous input signal and affects both ports.
A maser reset operation is required at power-up.
TRST
[2,5]
JTAG Reset Input
.
TMS
JTAG Test Mode Select Input
. It controls the advance of JTAG TAP state machine.
State machine transitions occur on the rising edge of TCK.
TDI
JTAG Test Data Input
. Data on the TDI input will be shifted serially into selected
registers.
TCK
JTAG Test Clock Input
.
TDO
JTAG Test Data Output
. TDO transitions occur on the falling edge of TCK. TDO
is normally three-stated except when captured data is shifted out of the JTAG TAP.
V
SS
Ground Inputs
.
INT
L
INT
R
LowSPD
L[2,4]
PORTSTD[1:0]
L[2,4]
R/W
L
LowSPD
R[2,4]
READY
L[2,5]
CNT/MSK
L[10]
ADS
L[11]
CNTEN
L[11]
CNTRST
L[10]
CNTINT
L[12]
WRP
L[2,3]
RET
L[2,3]
FTSEL
L[2,3]
VREF
L[2,4]
V
DDIOL
REV
L
[2, 3, 4]
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYD04S36V-133BBC 制造商:Cypress Semiconductor 功能描述:
CYD04S36V-133BBI 制造商:Cypress Semiconductor 功能描述:
CYD04S36V-167BBC 制造商:Cypress Semiconductor 功能描述:
CYD04S36V18 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mb/9-Mb/4-Mb x36/x18 FullFlex⑩ Dual-Ports
CYD04S36V18-167BBXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4M Sync Dual Port 128Kx36 90nm COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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