- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379098 > CYD04S36V (Cypress Semiconductor Corp.) FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36同步雙端口RAM) PDF資料下載
參數(shù)資料
| 型號： | CYD04S36V |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36同步雙端口RAM) |
| 中文描述： | FLEx36TM 3.3 32K/64K/128K/256K/512 × 36同步雙口RAM（FLEx36TM 3.3 32K/64K/128K/256K/512 × 36同步雙端口RAM）的 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 608K |
| 代理商： | CYD04S36V |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
CYD01S36V
CYD02S36V/CYD04S36V
CYD09S36V/CYD18S36V
Document #: 38-06076 Rev. *E
Page 14 of 28
t
SRST
t
HRST
t
SCM
t
HCM
t
OE
t
OLZ[31, 32]
t
OHZ[31, 32]
t
CD2
t
CA2
t
CM2
CNTRST Set-up Time
CNTRST Hold Time
CNT/MSK Set-up Time
CNT/MSK Hold Time
Output Enable to Data Valid
OE to Low Z
OE to High Z
Clock to Data Valid
Clock to Counter Address Valid
Clock to Mask Register Readback
Valid
Data Output Hold After Clock HIGH
t
CKHZ[31, 32]
Clock HIGH to Output High Z
t
CKLZ[31, 32]
Clock HIGH to Output Low Z
t
SINT
Clock to INT Set Time
t
RINT
Clock to INT Reset Time
t
SCINT
Clock to CNTINT Set Time
t
RCINT
Clock to CNTINT Reset time
Port to Port Delays
t
CCS
Clock to Clock Skew
Master Reset Timing
t
RS
Master Reset Pulse Width
t
RS
Master Reset Set-up Time
t
RSR
Master Reset Recovery Time
t
RSF
Master Reset to Outputs Inactive
t
RSINT
Master Reset to Counter and Mailbox
Interrupt Flag Reset Time
2.3
0.6
2.3
0.6
2.5
0.6
2.5
0.6
NA
NA
NA
NA
NA
NA
NA
NA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.0
4.4
5.5
5.5
0
0
0
0
0
0
0
0
4.0
4.0
4.0
4.0
4.4
4.4
4.4
4.4
5.5
5.0
NA
NA
5.5
5.2
NA
NA
t
DC
1.0
0
1.0
0.5
0.5
0.5
0.5
1.0
0
1.0
0.5
0.5
0.5
0.5
1.0
0
1.0
0.5
0.5
NA
NA
1.0
0
1.0
0.5
0.5
NA
NA
ns
ns
ns
ns
ns
ns
ns
4.0
4.0
6.7
6.7
5.0
5.0
4.4
4.4
7.5
7.5
5.7
5.7
4.7
4.7
7.5
7.5
NA
NA
5.0
5.0
10.0
10.0
NA
NA
5.2
6.0
5.7
8.0
ns
5.0
6.0
5.0
5.0
6.0
5.0
5.0
6.0
5.0
5.0
8.5
5.0
cycles
ns
cycles
ns
ns
10.0
10.0
10.0
10.0
10.0
NA
10.0
NA
Switching Characteristics
Over the Operating Range (continued)
Parameter
Description
-167
-133
-100
Unit
CYD01S36V
CYD02S36V
CYD04S36V
CYD09S36V
Min.
CYD01S36V
CYD02S36V
CYD04S36V
CYD09S36V
Min.
CYD18S36V
Min.
CYD18S36V
Min.
Max.
Max.
Max.
Max.
JTAG Timing
Parameter
f
JTAG
t
TCYC
t
TH
t
TL
t
TMSS
t
TMSH
Notes:
31.This parameter is guaranteed by design, but it is not production tested.
32.Test conditions used are Load 2.
Description
167/133/100
Min.
Unit
MHz
ns
ns
ns
ns
ns
Max.
10
Maximum JTAG TAP Controller Frequency
TCK Clock Cycle Time
TCK Clock HIGH Time
TCK Clock LOW Time
TMS Set-up to TCK Clock Rise
TMS Hold After TCK Clock Rise
100
40
40
10
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYD09S36V | FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36 Synchronous Dual-Port RAM(FLEx36TM 3.3V 32K/64K/128K/256K/512 x 36同步雙端口RAM) |
| CYD18S72V18 | FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM) |
| CYD04S72V18 | FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM) |
| CYD36S72V18 | FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM) |
| CYD09S72V18 | FullFlex Synchronous SDR Dual-Port SRAM(FullFlex同步SDR雙端口SRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYD04S36V-133BBC | 制造商:Cypress Semiconductor 功能描述: |
| CYD04S36V-133BBI | 制造商:Cypress Semiconductor 功能描述: |
| CYD04S36V-167BBC | 制造商:Cypress Semiconductor 功能描述: |
| CYD04S36V18 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:18-Mb/9-Mb/4-Mb x36/x18 FullFlex⑩ Dual-Ports |
| CYD04S36V18-167BBXC | 功能描述:靜態(tài)隨機存取存儲器 4M Sync Dual Port 128Kx36 90nm COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。