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參數(shù)資料
| 型號： | CYCLONE08UM |
| 英文描述： | MON08 Cyclone Users Manual |
| 中文描述： | 的MON08氣旋用戶手冊 |
| 文件頁數(shù)： | 31/64頁 |
| 文件大小： | 756K |
| 代理商： | CYCLONE08UM |
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MON08 Cyclone User Manual
29
P&E
Microcomputer
Systems, Inc.
MON08 CYCLONE
PORTA7, PORTC2, PORTC3 and PORTC4 are used for entering monitor
mode. By default the user may directly bring these signals out to the target
MON08 Header.
Alternatively, the user may pull up PORTC3, pull down PORTA7 and
PORTC4, and pull up/down PORTC2 for clock division. In which casethe user
does not need to connect these signals to the target MON08 Header.
Please note that the MR4/8 is not supported by the MON08 CYCLONE.
However, the MON08 MULTILINK by P&E does. Please refer to the MON08
MULTILINK user’s manual for detailed information.
3.22
68HC908QT
Figure 3-22: 68HC908QT Family MON08 Pinout
The target GND is connected to the Pin 2 of the target MON08 Header.
The user must pull up the RESET line to target VDD with an external resistor.
The target IRQ line is directly connected to the Pin 6 of the target MON08
Header.
PORTA0 from the target processor is connected to the target MON08 Header
Pin 8, acting as the communications line. The MON08 CYCLONE pulls up
this signal with a 10K Ohm resistor to the target VDD.
PORTA1 and PORTA4 are used for entering monitor mode. By default the user
may directly bring these signals out to the target MON08 Header.
Alternatively, the user may pull up PORTA1 and pull down PORTA4. In which
case the user does not need to connect these signals to the target MON08
Header. The clock division is fixed Div 4.
Please note that the CYCLONE will calculate the proper trim value for the
device being programmed and program this trim value to $FFC0.
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