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參數(shù)資料
| 型號(hào)： | CYK001M16SCCAU |
| 英文描述： | Memory |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 168K |
| 代理商： | CYK001M16SCCAU |
ADVANCE
INFORMATION
16-Mb (1M x 16) Pseudo Static RAM
CYK001M16SCCAU
MoBL
Cypress Semiconductor Corporation
Document #: 38-05426 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised January 8, 2004
Features
Advanced low power MoBL
architecture
High speed: 70 ns
Wide voltage range:
— V
CC
range: 2.7V to 3.3V
Low active power
— Typical active current: 2 mA @ f = 1 MHz
— Typical active current: 13 mA @ f = f
MAX
Low standby power
Automatic power-down when deselected
Functional Description
[1]
The CYK001M16SCCAU is a high-performance CMOS
pseudo static RAMs (PSRAM) organized as 1 Mb words by 16
bits that supports an asynchronous memory interface. This
device features advanced circuit design to provide ultra-low
active current. This is ideal for providing More Battery Life
(MoBL) in portable applications such as cellular telephones.
The device can be put into standby mode reducing power
consumption by more than 99% when deselected using CE
LOW, CE
2
HIGH or both BHE and BLE are HIGH. The
input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when: deselected (CE HIGH, CE
2
LOW
OE is deasserted HIGH), or during a write operation (Chip
Enabled and Write Enable WE LOW). The device also has an
automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling
even when the chip is selected (Chip Enable CE LOW, CE
2
HIGH and both BHE and BLE are LOW). Reading from the
device is accomplished by asserting the Chip Enables (CE
LOW and CE
2
HIGH) and Output Enable (OE) LOW while
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)
is LOW, then data from the memory location specified by the
address pins will appear on I/O
0
to I/O
7
. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O
8
to
I/O
15
. See the Truth Table for a complete description of read
and write modes.
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
1M x 16
RAM Array
1T
I/O
0
–I/O
7
COLUMN DECODER
S
DATA IN DRIVERS
OE
BLE
I/O
8
–I/O
15
WE
BHE
R
Power
-
Down
Circuit
BHE
BLE
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
A
1
A
1
A
1
A
1
A
1
A
1
A
1
A
1
A
1
CE
2
CE
CE
2
CE
Logic Block Diagram
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PDF描述 |
|---|---|
| CYK001M16ZCCAU | Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYK001M16SCCAU-55BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
| CYK001M16SCCAU-55BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 16MBIT 1MX16 55NS 48FBGA - Tape and Reel |
| CYK001M16SCCAU-70BAI | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 16MBIT 1MX16 70NS 48FBGA - Bulk |
| CYK001M16SCCAU-70BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 16MBIT 1MX16 70NS 48FBGA - Tape and Reel |
| CYK001M16ZCCA | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
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