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參數(shù)資料
| 型號(hào)： | CYK001M16SCCAU |
| 英文描述： | Memory |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 168K |
| 代理商： | CYK001M16SCCAU |
ADVANCE
INFORMATION
CYK001M16SCCAU
MoBL
Document #: 38-05426 Rev. **
Page 4 of 10
Thermal Resistance
[10]
AC Test Loads and Waveforms
Parameter
θ
JA
Description
Test Conditions
FBGA
55
Unit
°C/W
Thermal Resistance (Junction to
Ambient)
Thermal Resistance (Junction to
Case)
Still Air, soldered on a 3 x 4.5 inch, two-layer
printed circuit board
θ
JC
17
°C/W
Parameters
R1
R2
R
TH
V
TH
3.0V V
CC
1179
1941
733
1.87
Unit
V
Switching Characteristics
(Over the Operating Range)
[11]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
DBE
t
LZBE
t
HZBE
t
SK
Write Cycle
[14]
t
WC
t
SCE
Notes:
11. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of V
CC(typ)
/2, input pulse levels of 0V to V
CC(typ),
and output loading of
the specified I
OL
/I
OH
and 30-pF load capacitance
12.t
, t
, t
and t
transitions are measured when the outputs enter a high-impedance state.
13.High-Z and Low-Z parameters are characterized and are not 100% tested.
14.The internal write time of the memory is defined by the overlap of WE, CE
= V
, BHE and/or BLE =V
. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates write.
Description
CYK001M16SCCAU-70
Min.
Unit
Max.
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW and CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[12, 13]
OE HIGH to High Z
[12, 13]
CE LOW and CE
2
HIGH to Low Z
[12, 13]
CE HIGH and CE
2
LOW to High Z
[12, 13]
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[12, 13]
BLE/BHE HIGH to High-Z
[12, 13]
Address Skew
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
10
70
35
5
25
5
25
70
5
25
10
Write Cycle Time
CE LOW and CE
2
HIGH to Write End
70
55
ns
ns
VCC
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
OUTPUT
VTH
Equivalento:
THé ENINEQUIVALENT
RTH
ALL INPUT PULSES
R1
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|---|---|
| CYK001M16ZCCAU | Memory |
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| CYM1910PV-25C | SYNC SRAM|16KX68|CMOS|DIP|104PIN|PLASTIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYK001M16SCCAU-55BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
| CYK001M16SCCAU-55BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 16MBIT 1MX16 55NS 48FBGA - Tape and Reel |
| CYK001M16SCCAU-70BAI | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 16MBIT 1MX16 70NS 48FBGA - Bulk |
| CYK001M16SCCAU-70BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 16MBIT 1MX16 70NS 48FBGA - Tape and Reel |
| CYK001M16ZCCA | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
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