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參數(shù)資料
| 型號(hào)： | CYK001M16SCCAU |
| 英文描述： | Memory |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 168K |
| 代理商： | CYK001M16SCCAU |
ADVANCE
INFORMATION
CYK001M16SCCAU
MoBL
Document #: 38-05426 Rev. **
Page 6 of 10
Write Cycle No. 1(WE Controlled)
[14, 13, 16, 17, 18]
Write Cycle No. 2 (Chip Enable Controlled)
[14, 13, 16, 17, 18]
Notes:
16.Data I/O is high impedance if OE = V
.
17.If Chip Enable goes INACTIVE simultaneously with WE HIGH, the output remains in a high-impedance state.
18.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
Switching Waveforms
(continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
VALID DATA
CE
1
ADDRESS
CE2
WE
DATAI/O
OE
BHE
/
BLE
tBW
DON’T CARE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
VALID DATA
CE1
ADDRESS
CE2
WE
DATAI/O
OE
DON’T CARE
BHE/BLE
tBW
tSA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYK001M16ZCCAU | Memory |
| CYK512K16SCCAU | Memory |
| CYL2T0201-AIP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CYM1910PV-25C | SYNC SRAM|16KX68|CMOS|DIP|104PIN|PLASTIC |
| CYM1910PV-35C | SYNC SRAM|16KX68|CMOS|DIP|104PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYK001M16SCCAU-55BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
| CYK001M16SCCAU-55BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 16MBIT 1MX16 55NS 48FBGA - Tape and Reel |
| CYK001M16SCCAU-70BAI | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 16MBIT 1MX16 70NS 48FBGA - Bulk |
| CYK001M16SCCAU-70BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 16MBIT 1MX16 70NS 48FBGA - Tape and Reel |
| CYK001M16ZCCA | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
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