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參數(shù)資料
| 型號(hào)： | CYL2T0201-AIP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 32K |
| 代理商： | CYL2T0201-AIP |
ADVANCE
INFORMATION
MetroLink2T-2 Link Layer
CYL2T0201
Cypress Semiconductor Corporation
Document #: 38-02071 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Features
Maps two channels of Gigabit Ethernet (GbE), Fibre
Channel (1X, 1/2X, 1/4X), FICON
, or ESCON
indepen-
dently onto a SPI-3 interface for transparent transport
over SONET/SDH
—OC-48/STM-16, OC-12/STM-4 rates
—Compliant to draft recommendation of Transparent
Generic Framing Procedure (GFP-T) per the ITU-T
G.7041 (Version 0.4, October 2001)
Supports the following features to enable GFP-T
mapping of client payload of GbE, Fibre Channel, or
ESCON:
—Special character mapping
—Mapping and demapping into the GFP-T superblock
with a user-defined size
—Automatic 65B_PAD/10B_ERR character insertion
and deletion
—Client management frame (CMF) generation and
checking
Register programmable rate adaptation by
adding/removal of idle code sequences for:
—Gigabit Ethernet (IEEE 802.3z)
—Fibre Channel
—ESCON
—FICON
Programmable watermarks on each channel’s egress
FIFO to prevent overflow/underflow conditions by
enabling rate adaptation
Support for programmable interrupt generation on
error condition detection
32-bit host interface for register programming and
performance monitoring
Complete performance monitoring using error
counters in both egress and ingress directions
Programmable parity generation and checking on the
PHY and framer parallel interfaces
Programmable loopback functions for link verification
—SERDES interface loopback
—GFP-T mapper/demapper client-side loopback
1.8V core and 3.3V I/O supplies
Cypress GFP-T Transport Solution
MetroLink2T-2
, POSIC2G
/POSIC2GVC
,
and
HOTLink II
provide a complete end-to-end GFP-T solution
Provides seamless interface to Cypress POSIC2GVC
(CY7C9536) and POSIC2G (CY7C9537) to support:
—GFP-T frame delineation
—cHEC checking, calculation and scrambling
—Payload scrambling
—Idle frame insertion and deletion
Multiplexed CPU bus interface to POSIC2G/POSIC2GVC
(allows for a single CPU bus interface to both Metrolink2T
and POSIC2G/POSIC2GVC without external muxing)
Glueless parallel interface to Cypress HOTLink II trans-
ceivers to support:
—Clock and data recovery for GbE, Fibre Channel, and
ESCON
—Word framing
—8B/10B encoding and decoding
—Special character detection and flagging
Network Equipment
DWDM transport equipment
Multiservice provisioning platforms (MSPP)
SONET/SDH add/drop multiplexers (ADM)
SONET/SDH digital cross connects (DCS)
GbE,
FICON,
ESCON,
FC
Two-Channel
SERDES
CYP15G0201DX
8-bit data
bus, control
8-bit data
bus, control
SPI-3
Dual-Channel
GFP-T Mapper
CYL2T0201
OC-48/
STM-16
Framer
CY7C9536
OC-48/
STM-16
PHY
CYS25G0101DX
16-bit
HSTL
to optical
modules
Control CPU
CPU
Interface
POSIC2G/
POSIC2GVC
CPU Interface
Figure 1. MetroLink2T-2 Application
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