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參數(shù)資料
| 型號(hào)： | CY7C43646AV |
| 廠(chǎng)商： | Cypress Semiconductor Corp. |
| 英文描述： | 3.3V 1K 4K 16K x 36 x 18 x 2 Tri Bus FIFO |
| 中文描述： | 3.3每1000 4K的16K的× 36 × 18 × 2三總線(xiàn)先進(jìn)先出 |
| 文件頁(yè)數(shù)： | 37/40頁(yè) |
| 文件大?。?/td> | 644K |
| 代理商： | CY7C43646AV |
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CY7C43646AV
CY7C43666AV
CY7C43686AV
Document #: 38-06026 Rev. *C
Page 37 of 40
Notes:
69. If Port C is configured for word size, data can be written to the Mail2 register using C
0
–
17
. In this first case A
will have valid data (A
will be indeterminate).
If Port C is configured for byte size, data can be written to the Mail2 Register using C
0
–
8
(C
9
–
17
are
“
Don
’
t Care
”
inputs). In this second case, A
0
–
8
will have valid
data (A
will be indeterminate).
70. Retransmit is performed in the same manner for FIFO2.
71. Clocks are free running in this case. CY standard mode only. Write operation should be prohibited one Write clock cycle before the falling edge of RT1, and
during the retransmit operation, i.e, when RT1 is LOW and t
after the RT1 rising edge.
72. The Empty and Full flags may change state during Retransmit as a result of the offset of the Read and Write pointers, but flags will be valid at t
RTR
.
73. For the AEA, AEB, AFA, and AFC flags, two clock cycle are necessary after t
to update these flags.
74. The number of 36-/18-/9-bit words written into the FIFO should be less than full depth minus 2/4/8 words between the reset of the FIFO (master or partial) and
the Retransmit setup.
Switching Waveforms
(continued)
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)
[69]
t
ENH
t
ENS
t
DH
t
DS
W1
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENS
t
ENH
t
DIS
FIFO2 Output
Register
W1 (Remains valid in Mail2 Register after Read)
CLKC
MBC
WENC
C
0
–
17
CLKA
MBF2
CSA
W/RA
MBA
ENA
A
0
35
[37]
FIFO1 Retransmit Timing
RENB
RT1
t
RTR
EFB/FFA
[70, 71, 72, 73, 74]
t
RSTS
t
RST
CLKA
CLKB
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PDF描述 |
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| CY7C1360B-225AC | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| CY7C1360B-225BGC | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
| CY7C024AV-20AC | 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM |
| CY7C024AV-25AC | 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM |
| CY7C1360B-225AJI | 9-Mbit (256K x 36/512K x 18) Pipelined SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
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| CY7C43663-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43664-7AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43682-15AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683-10AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43683AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:3.3V SYNC FIFO W/BUS MATCHING 16K X36 (NOT IDT COMPAT) - Bulk |
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